Patents by Inventor Nazmul Habib
Nazmul Habib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11810832Abstract: A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.Type: GrantFiled: June 28, 2021Date of Patent: November 7, 2023Assignee: Marvell Asia Pte LtdInventors: Janak Patel, Richard Graf, Manish Nayini, Nazmul Habib
-
Patent number: 11682646Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.Type: GrantFiled: November 2, 2021Date of Patent: June 20, 2023Assignee: MARVELL ASIA PTE LTD.Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
-
Publication number: 20230035100Abstract: An electronic device, including a substrate and a stack of dies stacked on the substrate. The stack of dies includes: (a) one or more functional dies, the functional dies including functional electronic circuits and being configured to exchange electrical signals at least with the substrate, and (b) one or more dummy dies, the dummy dies being disposed among dies forming the stack and being configured to: (i) dissipate heat generated by the one or more functional dies and (ii) pass electrical signals exchanged between the substrate and the one or more functional dies or between two or more of the functional dies.Type: ApplicationFiled: July 27, 2022Publication date: February 2, 2023Inventors: Janak G. Patel, Manish Nayini, Richard S. Graf, Nazmul Habib
-
Publication number: 20220059488Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventors: Manish NAYINI, Richard S. GRAF, Janak G. PATEL, Nazmul HABIB
-
Publication number: 20210407879Abstract: A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.Type: ApplicationFiled: June 28, 2021Publication date: December 30, 2021Inventors: Janak PATEL, Richard GRAF, Manish NAYINI, Nazmul HABIB
-
Patent number: 11171104Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.Type: GrantFiled: October 24, 2019Date of Patent: November 9, 2021Assignee: MARVELL ASIA PTE, LTD.Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
-
Patent number: 11054459Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: GrantFiled: November 7, 2019Date of Patent: July 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Patent number: 10996259Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: GrantFiled: January 3, 2020Date of Patent: May 4, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Publication number: 20210125952Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.Type: ApplicationFiled: October 24, 2019Publication date: April 29, 2021Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
-
Patent number: 10989754Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: GrantFiled: November 16, 2017Date of Patent: April 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Patent number: 10794952Abstract: A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.Type: GrantFiled: June 13, 2018Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Jeanne Bickford, Theodoros Anemikos, Susan K. Lichtensteiger, Nazmul Habib
-
Patent number: 10700013Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.Type: GrantFiled: January 10, 2018Date of Patent: June 30, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams, Nazmul Habib
-
Publication number: 20200141996Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: ApplicationFiled: January 3, 2020Publication date: May 7, 2020Inventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Publication number: 20200072897Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Patent number: 10564214Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.Type: GrantFiled: June 22, 2017Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
-
Patent number: 10539611Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.Type: GrantFiled: November 3, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
-
Publication number: 20190214348Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams, Nazmul Habib
-
Patent number: 10216870Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.Type: GrantFiled: January 13, 2016Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeanne P. S. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
-
Patent number: 10168685Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.Type: GrantFiled: October 4, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Mark A. Burns, Douglas S. Dewey, Nazmul Habib, Daniel D. Reinhardt
-
Patent number: 10162325Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.Type: GrantFiled: October 10, 2016Date of Patent: December 25, 2018Assignee: International Business Machines CorporationInventors: Mark A. Burns, Douglas S. Dewey, Nazmul Habib, Daniel D. Reinhardt