Abstract: A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighboring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated.

Abstract: A digital computer can write a block of data to a RAM, or read a block therefrom, via a serial/parallel converter which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter clocked by clock pulses WCK. A fault masking circuit enables faulty cells in the RAM to be masked out. Data specific to the RAM causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter. These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs served by a single fault masking circuit with tabulated data defining the memory cells to be masked out on a memory by memory basis.