Abstract: A multi-user host computer system comprises a host computer that processes applications and the desktop environments for multiple remote terminals. The host computer includes a terminal services offload processor to supplement the processing of the host CPU. For each remote terminal, the terminal services offload processor may improve the video and graphics performance and allow the multi-user host computer system to more efficiently support multiple users. The host computer may include a graphics processor that manages a virtual display for each remote terminal and provides selective updates of sub frame data. Where appropriate, the sub frame data is encoded and transmitted over the network to the remote terminals. Video data streams are also optimized by the terminal services offload processor and optimized for the intended remote terminals and their respective network connections.

Abstract: A digital display system consists of an image modulator and multiple light modulators. An image processing system processes an incoming data stream, scans processed data to an image modulator and controls for the light modulators. Other user inputs and sensors are used to affect the processing and controls. The timing for scanning the processed data into the image modulators is controlled along with the intensity and wavelength of the light modulators. The display system may implement a spatial and temporal image processing, digital shutter controls, rolling shutter controls, sequential color output, adaptive dynamic sensor feedback, frame rate matching, motion compensated field sequencing and a variety of other techniques to produce a high quality display output. The resulting display has improved image consistency, enhanced color gamut, higher dynamic range and is better able to portray high motion content.

Abstract: Image processing enhances display quality by controlling both the image modulator and the light sources to produce the best possible visual images. The image processing system utilizes a combination of user inputs, system configuration, design information, sensor feedback, pixel modulation information, and lighting control information to characterize the display environment on a per pixel basis. This per pixel characterization information is combined with one or more frames of the incoming real time display data. The image processing system processes each incoming pixel and produces a modified corresponding output pixel. Each pixel of each frame is processed accordingly. In addition to producing modified output pixels, the image processing system produces control information for the light sources. The light source control information can control individual lamps, tubes or LEDs, or can control a block or subset of the light sources.

Abstract: A multi-display system includes a host system that supports both graphics and video based frames for multiple remote displays, multiple users or a combination of the two. For each display and for each frame, a multi-display processor responsively manages each necessary aspect of the remote display frame. The necessary portions of the remote display frame are further processed, encoded and where necessary, transmitted over a network to the remote display for each user. In some embodiments, the host system manages a remote desktop protocol and can still transmit encoded video or encoded frame information where the encoded video may be generated within the host system or provided from an external program source.

Abstract: A method for effectively implementing a multi-room television system includes a digital base station that processes and combines various program sources to produce a processed stream. A communications processor then responsively transmits the processed stream as a local composite output stream to various wired and wireless display devices for flexible viewing at variable remote locations. The transmission path performance is used to determine the video encoding process, and special attention is taken to assure that all users have low-latency interactive capabilities.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: An image processing apparatus for use in a display system comprises a display device for viewing image, and a geometric transformation module that is configured to precondition said image data with geometric transformations to thereby compensate for characteristics of the display system. The geometric transformation module may include a spatial transformation module for redefining spatial relationships between image pixels, an alignment and rotation correction module for repositioning image pixels, a focus correction module for correcting image defocus, a distortion correction module for correcting image distortions, and a multi-frame correlation module for performing motion-compensated frame rate conversion.

Abstract: An image processing apparatus for use in a display system comprises a display device for viewing image, and a geometric transformation module that is configured to precondition said image data with geometric transformations to thereby compensate for characteristics of the display system. The geometric transformation module may include a spatial transformation module for redefining spatial relationships between image pixels, an alignment and rotation correction module for repositioning image pixels, a focus correction module for correcting image defocus, a distortion correction module for correcting image distortions, and a multi-frame correlation module for performing motion-compensated frame rate conversion.

Abstract: An image processing system including a display output processor using Temporal Gamma Processing (TGP) and Reverse Super-resolution (RSR) techniques to process images. TGP assures that the time-related representation of an image is as accurate as possible, and thus, based on a previous frame value and a known transfer function of the display modulation system, adjusts its output values to provide a desired output value during display of a desired frame. RSR performs a superset of the frame rate conversion process for converting between disparate input and output frame rates. RSR, improving display quality when intended display images have apparent resolution higher than can be supported by an image modulator, sequences lower resolution images at higher frame rates to simulate higher resolution outputs.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: An apparatus and method for effectively implementing a wireless television system may include a communications processor and a transmitter device that combine at least one of a local-area network interface, a wide-area network interface, and one or more television data interfaces for effectively performing a wireless network transmission process. A transmitted stream from the wireless television system may be received via wireless network processing for viewing local-area network data, wide-area network data (such as Internet data), or television data by flexibly utilizing various electronic devices such as a notepad personal computer, a personal digital assistant (PDA), or a handheld TV remote control device.

Abstract: A method for effectively implementing a wireless television system comprises a wireless base station that processes and combines various program sources to produce a processed stream. A transmitter then responsively transmits the processed stream as a broadcast output stream to various portable wireless display devices for flexible viewing at variable remote locations.

Abstract: An image processing system using bitstream information for enhancing visual display quality. The processing system retains I frames and some P or B frames from a standard MPEG-2 bitstream, and stores the information across multiple Groups of Pictures (GOPs). The system uses prediction block information in conjunction with detected object edges and bitstream vector information to analyze object optical flow and to reconstruct high quality image frames. The system can also utilize supplemental bitstream information such as layer coding, instructional cues, and image key meta data to further improve the quality of the image frames and for special system functions. When an input image does not include MPEG-2 motion vector bitstream information, the system uses techniques such as optical flow, block matching, or Pel-recursion to estimate motion that tracks the image object motion.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: A memory architecture having one or more shared high-bandwidth memory subsystems each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. The display subsystem receives data from the high-speed shared memory for processing various video and graphics data types for display refresh. Additional buffers and caches are used for the subsystems to further optimize system performance. The display refresh path includes processing of the data from the memory subsystem for output to the display where the data enters the shared memory from an I/O subsystem or from the CPU subsystem.

Abstract: A method for signaling the type of access sought by a microprocessor to external memory. A microprocessor can read from or write into external memory. When the microprocessor initiates a read or write cycle, access signals indicating: the read or write cycle, the lower order address bits of the sought after code or data, whether code or data is sought, and bit-width of the sought after code or data, are provided to the inventions byte enable chaser circuit. If a read cycle has been initiated the byte enable chaser circuit encodes the signals into predetermined bit patterns and outputs the bit patterns on the microprocessor's byte enable signal pins. The bit-patterns are available for each bus cycle and specify whether code or data is sought, the length of the sought string, and the lower order address bits of the strings address. If a write cycle is initiated the byte enable signed pins indicate which byte(s) of the data bus are to be written into memory.