Abstract: A network interface device (15a) has a mass storage device interface (3a), which emulates a hard disk controller to transfer network traffic between a node (Ia) and the network. As a result, the node (Ia), typically a computer, is presented with a virtual hard disk (4a), which network traffic (e.g. data) can be written to and read from using standard hard disk protocols, e.g. SATA or PATA. In a computer cluster (13), several network interface devices (15a-15c) may be integrated in a router (8) having a switch (9). The router may connect to optional components such as hard disks (17a, 17b), a processor (18) and a Ethernet connection (19).

Abstract: A network interface device (15a) has a mass storage device interface (3a), which emulates a hard disk controller to transfer network traffic between a node (Ia) and the network. As a result, the node (Ia), typically a computer, is presented with a virtual hard disk (4a), which network traffic (e.g. data) can be written to and read from using standard hard disk protocols, e.g. SATA or PATA. In a computer cluster (13), several network interface devices (15a-15c) may be integrated in a router (8) having a switch (9). The router may connect to optional components such as hard disks (17a, 17b), a processor (18) and a Ethernet connection (19).

Abstract: The present invention relates to a cache (10) and system and method of maintaining cache coherency in a parallel processing system, by tagging (13) cached data (11) with the identity of the users or process threads which have access rights to the data. Cache users may see a cache miss even if the data is in the cache, unless they have access rights. The tags can be reset to disallow further access on thread transfer or at the point of synchronisation of process threads.

Abstract: The present invention relates to a system and method of distributing workload among processors (11) in a multi-processor system (10), with workload being transferred through a plurality of transfers between processor pairs (12), such that the plurality of pairs together define a closed loop. The present invention enables a processor to automatically balance its workload with other similar processors connected to it, with minimal interprocessor connection.

Abstract: The present invention describes a multi-processor computer system (10) based on dataflow principles. The present invention relates to distributed processing in a shared memory computer and provides a memory controller (14) that is able to perform logical and arithmetic operations on memory (15) on behalf of a processor (11), each memory leaf having its own controller. A processor need only make a single memory transaction to perform complex operations and does not need critical sections in order to resolve memory contention.

Abstract: The present invention relates to a cache (10) and system and method of maintaining cache coherency in a parallel processing system, by tagging (13) cached data (11) with the identity of the users or process threads which have access rights to the data. Cache users may see a cache miss even if the data is in the cache, unless they have access rights. The tags can be reset to disallow further access on thread transfer or at the point of synchronisation of process threads.