Patents by Inventor Nebojsa Makljenovic

Nebojsa Makljenovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9965342
    Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: May 8, 2018
    Assignee: ARM Limited
    Inventors: John Michael Horley, Nebojsa Makljenovic, Katherine Elizabeth Kneebone, Michael John Williams, Ian William Spray
  • Patent number: 9953444
    Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 24, 2018
    Assignee: ARM Limited
    Inventors: Isidoros Sideris, Michel Patrick Gabriel Emil Iwaniec, Andrew Burdass, Nebojsa Makljenovic, Andreas Due Engh-Halstvedt
  • Patent number: 9411662
    Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 9, 2016
    Assignee: ARM Limited
    Inventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Due Engh-Halstvedt
  • Publication number: 20160110837
    Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 21, 2016
    Inventors: Isidoros SIDERIS, Michel Patrick Gabriel Emil IWANIEC, Andrew BURDASS, Nebojsa MAKLJENOVIC, Andreas Due ENGH-HALSTVEDT
  • Patent number: 8966494
    Abstract: A data processing apparatus has processing circuitry for processing threads using resources accessible to the processing circuitry. Thread handling circuitry handles pending threads which are waiting for resources required for processing. When a request is made for a resource which is not available, a lock is set to ensure that once the resource becomes available, the resource remains available until the lock is removed. This prevents other threads reallocating the resource. When a subsequent pending thread requests access to the same locked unavailable resource, the lock is transferred to that subsequent thread so that the latest thread accessing that resource is considered the lock owning thread. The lock is removed once the lock owning thread is ready for processing.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: February 24, 2015
    Assignee: ARM Limited
    Inventors: Nebojsa Makljenovic, Benjamin Charles James
  • Patent number: 8589934
    Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: November 19, 2013
    Assignee: ARM Limited
    Inventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Engh-Halstvedt
  • Publication number: 20130305255
    Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
    Type: Application
    Filed: July 16, 2013
    Publication date: November 14, 2013
    Applicant: ARM Limited
    Inventors: Nebojsa MAKLJENOVIC, Edvard FIELDING, Andreas Due ENGH-HALSTVEDT
  • Publication number: 20130247060
    Abstract: A data processing apparatus has processing circuitry for processing threads using resources accessible to the processing circuitry. Thread handling circuitry handles pending threads which are waiting for resources required for processing. When a request is made for a resource which is not available, a lock is set to ensure that once the resource becomes available, the resource remains available until the lock is removed. This prevents other threads reallocating the resource. When a subsequent pending thread requests access to the same locked unavailable resource, the lock is transferred to that subsequent thread so that the latest thread accessing that resource is considered the lock owning thread. The lock is removed once the lock owning thread is ready for processing.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: ARM LIMITED
    Inventors: Nebojsa MAKLJENOVIC, Benjamin Charles JAMES
  • Publication number: 20120254882
    Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Applicant: ARM LIMITED
    Inventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Due Engh-Halstvedt
  • Publication number: 20110231691
    Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 22, 2011
    Applicant: ARM Limited
    Inventors: John Michael Horley, Nebojsa Makljenovic, Katherine Elizabeth Kneebone, Michael John Williams, Ian William Spray