Patents by Inventor Nedal R. Saleh

Nedal R. Saleh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9091942
    Abstract: A system and method for assessing line edge roughness (LER) is disclosed. An artificial conformal liner on a simulation test structure absorbs the same amount of light that otherwise would be scattered in the dark-field by a rough surface. A RCWA based scatterometry model is used to model absorption and the absorption is correlated to line edge roughness, which allows RCWA to be used in effect to model LER.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventor: Nedal R. Saleh
  • Patent number: 8860956
    Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nedal R. Saleh, Yunlin Zhang
  • Publication number: 20140268181
    Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nedal R. Saleh, Yunlin Zhang
  • Publication number: 20140073114
    Abstract: Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicants: GlobalFoundries Inc., International Business Machines Corporation
    Inventors: Cheng Cen, Steven B. Herschbein, Narender Rana, Nedal R. Saleh, Alok Vaid
  • Publication number: 20130200501
    Abstract: Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Cen, Steven B. Herschbein, Narender Rana, Nedal R. Saleh, Alok Vaid
  • Publication number: 20130132036
    Abstract: A system and method for assessing line edge roughness (LER) is disclosed. An artificial conformal liner on a simulation test structure absorbs the same amount of light that otherwise would be scattered in the dark-field by a rough surface. A RCWA based scatterometry model is used to model absorption and the absorption is correlated to line edge roughness, which allows RCWA to be used in effect to model LER.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nedal R. Saleh