Abstract: A voltage regulator includes a current bridge and first and second current paths coupling a current mirror to respective first and second voltage-to-current converters. The current mirror controls a second current dependent on a first current. The first voltage-to-current converter controls the first current dependent on either a reference voltage or a feedback voltage derived from the regulator's output voltage, and the second voltage-to-current converter controls the second current dependent on the other of the feedback and reference voltages. Voltage-to-current conversion by the first converter is independent of voltage-to-current conversion by the second converter. An output transistor stage coupled to the second current path controls the output voltage dependent on the voltage in the second current path indicative of a deviation of the second current from a target current value dependent on the reference voltage.

Abstract: An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude.

Abstract: An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude.

Abstract: An electronic device (100) comprises an integrated circuit die (130) mounted on a substrate (120). An electrical terminal (134) of the integrated circuit die (130) is coupled to an electrical terminal (124) of the substrate (120) by means of a wire (136) embedded in an electrically non-conductive moulded housing (140). The integrated circuit die (130) is also embedded in the electrically non-conductive moulded housing (140). There is an electrically conductive material (146) on a surface (142) of the moulded housing (140), and a connection means (127) for coupling the electrically conductive material (146) to a reference voltage. The electrically conductive material (146) and the substrate (120) in combination enclose the first integrated circuit die (130) and the first wire (136). There is a second integrated circuit die (150) mounted on the first electrically conductive material (146) and separated from the first wire (136) by the first electrically conductive material (146).

Abstract: An integrated circuit package including: a substrate having front connection pads on a front face, an integrated circuit die linked to the front face of the substrate and having front connection pads, connection wires for connecting selected front pads of the integrated circuit die to selected front pads of the substrate, first connection balls on selected front connection pads of the integrated circuit die, and second connection balls on selected front connection pads of the substrate. An integrated circuit device including a second substrate connected to the connection balls of the integrated circuit package.

Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.

Abstract: An integrated circuit device or package comprising: a laminated substrate, at least an electro-optical element at least partially inserted in the laminated substrate, and at least an optical wave-guide element at least partially inserted in the laminated substrate and optically coupled to the electro-optical element. An integrated circuit system comprising an integrated circuit device and a mounting plate carrying an optical wave-guide part or fiber.

Abstract: An integrated circuit package including: a substrate having front connection pads on a front face, an integrated circuit die linked to the front face of the substrate and having front connection pads, connection wires for connecting selected front pads of the integrated circuit die to selected front pads of the substrate, first connection balls on selected front connection pads of the integrated circuit die, and second connection balls on selected front connection pads of the substrate. An integrated circuit device including a second substrate connected to the connection balls of the integrated circuit package.

Abstract: An optical device for an integrated circuit device, includes a laminated substrate having a through-passage and a tubular frame in which an optical lens is mounted, the tubular frame having an end part inserted or integrated in the through-passage of the laminated substrate. A integrated circuit device includes an optical device and an integrated circuit die carried by the laminated substrate and having an active optical area placed in front of the optical lens.

Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.