Patents by Inventor Neeraj Kaul
Neeraj Kaul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10237254Abstract: The present disclosure relates to a system and method for providing conditional login promotion. An example system includes at least one processor and at least one memory element, wherein the system is configured for receiving an indication of a local operating system login by a user from a client device associated with the user; receiving one or more authentication factors associated with the user from the client device; and determining whether the local operating system login is to be promoted to a relying party entity based upon the one or more authentication factors associated with the user.Type: GrantFiled: March 27, 2015Date of Patent: March 19, 2019Assignee: McAfee, LLCInventors: John R. McDowell, Neeraj Kaul, Pavan Kumar V. Bharathapudi, Siddaraya B. Revashetti, Ranjit S. Narjala, Ramkumar Ram Chary Venkatachary, Sahar Mostafa, Vani Yalapalli, Charles Slate
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Publication number: 20160330183Abstract: The present disclosure relates to a system and method for providing conditional login promotion. An example system includes at least one processor and at least one memory element, wherein the system is configured for receiving an indication of a local operating system login by a user from a client device associated with the user; receiving one or more authentication factors associated with the user from the client device; and determining whether the local operating system login is to be promoted to a relying party entity based upon the one or more authentication factors associated with the user.Type: ApplicationFiled: March 27, 2015Publication date: November 10, 2016Applicant: McAfee, Inc.Inventors: John R. McDowell, Neeraj Kaul, Pavan Kumar V. Bharathapudi, Siddaraya B. Revashetti, Ranjit S. Narjala, Ramkumar Ram Chary Venkatachary, Sahar Mostafa, Vani Yalapalli, Charles Slate
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Patent number: 8037442Abstract: One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size.Type: GrantFiled: November 26, 2008Date of Patent: October 11, 2011Assignee: Synopsys, Inc.Inventors: Peiqing Zou, Douglas Chang, Neeraj Kaul
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Patent number: 8001514Abstract: One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an estimation of a number of route overflows for routing layers in a region of the circuit layout. Furthermore, a respective routing layer is associated with a preferred direction variable D. Next, the system transfers an overflow value k in direction d away from an overflowing routing layer for the first local routing region to a second local routing region, which has the capacity to handle an overflow of k or more routes in a direction d. Finally, the system computes a global routability estimation as a function of a global overflow cost and an adjacent overflow cost.Type: GrantFiled: April 23, 2008Date of Patent: August 16, 2011Assignee: Synopsys, Inc.Inventors: Douglas Chang, Neeraj Kaul, Balkrishna Rashingkar
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Publication number: 20100131913Abstract: One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size.Type: ApplicationFiled: November 26, 2008Publication date: May 27, 2010Applicant: SYNOPSYS, INC.Inventors: Peiqing Zou, Douglas Chang, Neeraj Kaul
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Publication number: 20090271754Abstract: One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an estimation of a number of route overflows for routing layers in a region of the circuit layout. Furthermore, a respective routing layer is associated with a preferred direction variable D. Next, the system transfers an overflow value k in direction d away from an overflowing routing layer for the first local routing region to a second local routing region, which has the capacity to handle an overflow of k or more routes in a direction d. Finally, the system computes a global routability estimation as a function of a global overflow cost and an adjacent overflow cost.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Applicant: SYNOPSYS, INC.Inventors: Douglas Chang, Neeraj Kaul, Balkrishna Rashingkar
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Patent number: 7313776Abstract: A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit based on the location of pins associated with the net. Next, the system generates routing constraints for each net based on the classification of the net and applies a feedthrough constraint to the physical partitions to restrict nets from feeding through physical partition boundaries. Finally, the system routes each net using the routing constraints for the net and the feedthrough constraints for the physical partitions. This routing is performed based on these block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.Type: GrantFiled: June 28, 2005Date of Patent: December 25, 2007Assignee: Synopsys, Inc.Inventors: Neeraj Kaul, Balkrishna Rashingkar, Anthony Y. Tseng, Wei-Chih Tseng
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Publication number: 20060294485Abstract: A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit based on the location of pins associated with the net. Next, the system generates routing constraints for each net based on the classification of the net and applies a feedthrough constraint to the physical partitions to restrict nets from feeding through physical partition boundaries. Finally, the system routes each net using the routing constraints for the net and the feedthrough constraints for the physical partitions. This routing is performed based on these block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Inventors: Neeraj Kaul, Balkrishna Rashingkar, Anthony Tseng, Wei-Chih Tseng
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Patent number: 5596585Abstract: A methodology for selecting an optimal group of flip-flops in a circuit design to be converted into BIST elements is disclosed which minimizes the performance degradation resulting from such conversion. In accordance with the present invention, the additional timing delays introduced into the circuit design resulting from each conversion of a flip-flop into a BIST element is incorporated into the selection of those flip-flops to be converted such that only those flip-flops which may be converted without any resultant timing violations are deemed suitable for conversion. A minimum group of these "suitable" flip-flops which breaks all of the logic cycles in the circuit is then selected for BIST conversion. Thus, selection methodologies in accordance with the present invention not only simultaneously minimizes the increase in silicon area due to BIST conversion while maximizing fault coverage, but also results in minimal performance degradation.Type: GrantFiled: June 7, 1995Date of Patent: January 21, 1997Assignee: Advanced Micro Devices, Inc.Inventors: Charles A. Njinda, Neeraj Kaul