Patents by Inventor Neil Bailey
Neil Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168734Abstract: A method, computer program product, and computer system for identifying involvement of application services in a distributed application. The method includes accessing traced request data of application requests for a distributed application and determining dependencies and call frequency between application services from the traced request data of the application requests. The method includes obtaining an involvement factor of an application service as a measure of involvement of the application service in the application requests based on the dependencies and call frequencies. The method applies the involvement factor to availability and functioning management of the distributed application.Type: ApplicationFiled: November 21, 2022Publication date: May 23, 2024Inventor: Christopher Neil Bailey
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Patent number: 11983201Abstract: Concepts for creating a metatype tree for metatype introspection are presented. One example comprises decoding a parent metatype from a synthetic dataset by decoding one or more child metatypes of the parent metatype. The method then comprises creating a metatype tree comprising a parent node and one or more child nodes of the parent node. The parent node comprises the decoded parent metatype and the one or more child nodes of the parent node comprise the one or more decoded child metatypes.Type: GrantFiled: September 27, 2019Date of Patent: May 14, 2024Assignee: International Business Machines CorporationInventors: Enrique Lacal Bereslawski, Ian Partridge, Christopher Neil Bailey, Neil Hardman
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SYSTEMS AND METHODS FOR COORDINATING PROCESSING OF SCHEDULED INSTRUCTIONS ACROSS MULTIPLE COMPONENTS
Publication number: 20240104657Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicant: Chicago Mercantile Exchange Inc.Inventors: Zachary Bonig, Eric Thill, Pearce Peck-Walden, José Antonio Acuña-Rohter, Barry Galster, Neil Steuber, James Bailey, Jake Siddall -
Publication number: 20240070687Abstract: A processing module may be centralized and coupled to multiple inputs from customers, and behave deterministically, e.g., programmed to depend on state, inputs and outputs. The rapid speed of automated trading systems implementing such a centralized, deterministic module, where all users can access a central limit order object, can quickly result in an object state that does not reflect a true consensus or desirable state. Accordingly the resulting problem is a problem arising in computer systems due in part to the high speeds of computer systems. The solutions disclosed herein are, in one embodiment, implemented as automatic responses and actions by a computing system.Type: ApplicationFiled: October 19, 2023Publication date: February 29, 2024Applicant: Chicago Mercantile Exchange Inc.Inventors: Neil A. Lustyk, John Scheerer, James Bailey, Paul Millhuff
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Patent number: 11785115Abstract: Embodiments of the present invention provide concepts for tracing a request in a distributed system architecture comprising one or more distributed services. A request is received at a network traffic component on one of a plurality of sockets, which are monitored by a span correlation component. Span data is obtained from the received request and a process identification component is adapted to identify a process associated with the request based on the span data. The span correlation component is adapted to identify a socket connection made by the identified process and correlate the socket connection with the span data, thereby generating span correlation data.Type: GrantFiled: September 27, 2021Date of Patent: October 10, 2023Assignee: International Business Machines CorporationInventor: Christopher Neil Bailey
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Patent number: 11683391Abstract: A method, system, and computer program product for predicting microservices required for incoming requests for reducing the start latency of serverless microservices. The method may include obtaining tracing data of microservices of an application for historical requests processed by the application. The method may also include grouping the tracing data based on common request attributes. The method may also include aggregating each group into rules relating the common request attributes to lists of microservices. The method may also include building a predictive model formed of the rules for processing incoming requests to obtain a list of predicted microservices required for the incoming request based on attributes of the incoming request.Type: GrantFiled: September 10, 2021Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Matthew Paul Wilson, David Richard Jones, Sandra Hayward, Johanna Saladas Zaaijer, Christopher Neil Bailey, Ian Partridge
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Publication number: 20230101915Abstract: Embodiments of the present invention provide concepts for tracing a request in a distributed system architecture comprising one or more distributed services. A request is received at a network traffic component on one of a plurality of sockets, which are monitored by a span correlation component. Span data is obtained from the received request and a process identification component is adapted to identify a process associated with the request based on the span data. The span correlation component is adapted to identify a socket connection made by the identified process and correlate the socket connection with the span data, thereby generating span correlation data.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventor: Christopher Neil Bailey
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Publication number: 20230088581Abstract: A method, system, and computer program product for predicting microservices required for incoming requests for reducing the start latency of serverless microservices. The method may include obtaining tracing data of microservices of an application for historical requests processed by the application. The method may also include grouping the tracing data based on common request attributes. The method may also include aggregating each group into rules relating the common request attributes to lists of microservices. The method may also include building a predictive model formed of the rules for processing incoming requests to obtain a list of predicted microservices required for the incoming request based on attributes of the incoming request.Type: ApplicationFiled: September 10, 2021Publication date: March 23, 2023Inventors: Matthew Paul Wilson, David Richard Jones, Sandra Hayward, Johanna Saladas Zaaijer, Christopher Neil Bailey, Ian Partridge
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Publication number: 20220257166Abstract: A garment or a sleeve for being worn by an animal, the garment or sleeve comprising: a structure of a flexible material; a plurality of electrical connectors for mechanically and electrically coupling to a sensing device, the connectors being attached to the structure; and a plurality of electrodes printed on a surface of the structure, each electrode being in electrical communication with a respective one of the connectors.Type: ApplicationFiled: July 17, 2020Publication date: August 18, 2022Inventors: David FROST, Neil BAILEY
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Publication number: 20220253347Abstract: A process or may reduce start latency of serverless microservices. The processor may detect an incoming request or event to an application in a serverless microservice environment. The incoming request or event may initiate a chain of invocations of one or more microservices of the application. The processor may select an amount of selected microservices from the one or more microservices of the application. The amount of selected microservices may perform a task of the incoming request or event. The task may apply one or more predefined application-specific rules to one or more elements of the incoming request or event to determine the amount of selected microservices. The processor may trigger scaling up activation of the one or more microservices of the application. The processor may invoke the one or more microservices of the application to match the amount of selected microservices.Type: ApplicationFiled: February 10, 2021Publication date: August 11, 2022Inventors: David Richard Jones, IAN PARTRIDGE, Christopher Neil Bailey, Sandra Hayward, Johanna Saladas Zaaijer, Matthew Paul Wilson
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Publication number: 20210097090Abstract: Concepts for creating a metatype tree for metatype introspection are presented. One example comprises decoding a parent metatype from a synthetic dataset by decoding one or more child metatypes of the parent metatype. The method then comprises creating a metatype tree comprising a parent node and one or more child nodes of the parent node. The parent node comprises the decoded parent metatype and the one or more child nodes of the parent node comprise the one or more decoded child metatypes.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: ENRIQUE LACAL BERESLAWSKI, IAN PARTRIDGE, Christopher Neil Bailey, NEIL HARDMAN
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Publication number: 20200285530Abstract: Concepts for middleware in a web framework are presented. One example comprises defining a target object type configured to hold results of a middleware function. A first object for an application is received and a process of the middleware function is performed, using the first object, to generate a process result. Based on the process result, a second object of the target object type is generated, after which the second object is provided to the application.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Andrew Michael Lees, David Richard Jones, Christopher Neil Bailey, Ian Partridge
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Patent number: 9763270Abstract: A method for establishing a communication link between two devices, the communication link employing a protocol that provides for link establishment information sufficient for establishing a link between two devices to be negotiated between those devices; the method comprising: establishing communication links between each of the two devices and one or more further devices; transmitting from the one or more further devices to each of the two devices information that defines link establishment parameters for a link between the two devices; and establishing the link between the two devices using the defined link establishment parameters.Type: GrantFiled: January 11, 2011Date of Patent: September 12, 2017Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.Inventor: Neil Bailey
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Patent number: 9397961Abstract: A method of remapping allocated memory in a queue based switching element having first and second memory elements each allocated to a first port pair. An unallocated block of memory is identified in the first memory element as a candidate block, and an allocated block of memory is identified in the second memory element as a target block. Block information is copied from the target block to the candidate block, and the candidate block is maintained as unallocated. In response to a determination that read and write pointers are in a suitable position for a remapping operation, the candidate block is allocated and the target block is deallocated so that the second memory element becomes unallocated and available for reallocation to a second port pair.Type: GrantFiled: September 20, 2013Date of Patent: July 19, 2016Assignee: Microsemi Storage Solutions (U.S.), Inc.Inventor: Patrick Neil Bailey
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Patent number: 8832412Abstract: Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.Type: GrantFiled: September 20, 2011Date of Patent: September 9, 2014Assignee: Broadcom CorporationInventors: Neil Bailey, Eben Upton
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Publication number: 20130024652Abstract: Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.Type: ApplicationFiled: September 20, 2011Publication date: January 24, 2013Applicant: BROADCOM CORPORATIONInventors: Neil Bailey, Eben Upton
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Patent number: 8285975Abstract: A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.Type: GrantFiled: April 15, 2003Date of Patent: October 9, 2012Assignee: Broadcom Europe LimitedInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20120030465Abstract: A method for establishing a communication link between two devices, the communication link employing a protocol that provides for link establishment information sufficient for establishing a link between two devices to be negotiated between those devices; the method comprising: establishing communication links between each of the two devices and one or more further devices; transmitting from the one or more further devices to each of the two devices information that defines link establishment parameters for a link between the two devices; and establishing the link between the two devices using the defined link establishment parameters.Type: ApplicationFiled: January 11, 2011Publication date: February 2, 2012Applicant: CAMBRIDGE SILICON RADIO LIMITEDInventor: Neil Bailey
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Publication number: 20110249744Abstract: A multimedia processor may comprise a first scalar core, a second scalar core, and a vector core integrated on a single substrate of said multimedia processor. The multimedia processor may receive data and instructions associated with image processing. The multimedia processor may configure the received data and instructions into data and instructions associated with a first image processing program and into data and instructions associated with a second image processing program independent of the first image processing program. The first image processing program may be configured to be handled by the first scalar core and the vector core, while the data and instructions associated with the second image processing program may be configured to be handled by the second scalar core and the vector core. The vector core may communicate data to and from register files in each of the first and second scalar cores.Type: ApplicationFiled: December 23, 2010Publication date: October 13, 2011Inventor: Neil Bailey
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Patent number: 7818540Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.Type: GrantFiled: May 19, 2006Date of Patent: October 19, 2010Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann