Abstract: A configuration for FPGA logic is provided to perform random access channel (RACH) preamble detection used in 3G mobile communications to identify individual rows of a Hadamard matrix using a Walsh Hadamard Transform (WHT). The configuration provides minimal add/subtract circuit blocks for the WHT by using stages, each stage containing a shift register connected to an add/subtract circuit. The shift register has outputs provided from a tap into its nth and n/2 elements, the outputs being connected to an add/subtract circuit, wherein n is the order of the Hadamard matrix. In a further embodiment parallel connected shift registers are used in each stage to increase operation speed.

Abstract: A circuit to generate Orthogonal Variable Spread Factor (OVSF) codes for CDMA systems. The circuit includes a shift register to determine the OVSF code k for a given spread factor SF, wherein k ranges between 0 and (SF?1). A memory cell register stores the leftmost bit of the code that is loaded into the first bit of the shift register. An XOR gate provides an input to the shift register after the first bit is loaded from the memory cell. An address Look Up Table (LUT), or state machine, is connected to the shift register to select a tap output from one of the shift register bits to provide a first input to the XOR gate. A secondary OVSF code register connects to a second input of the XOR gate to provide code bits from lower SF values making up the code from the current SF value.

Abstract: Method and apparatus for signal reflection removal, such as echo cancellation, is described. Signal samples are delayed. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a communication network, such as in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. Echo cancellers described herein can be implemented in an FPGA. Echo in over a thousand channels can be cancelled using an FPGA and an external memory device. In embodiments for reflected signal cancellation, multiple stages of echo estimation are used.

Abstract: An algorithm that includes delay elements is used for echo cancellation. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. This algorithm can be advantageously implemented in FPGAs. Echo in over a thousand channels can be cancelled using a FPGA and an external memory device.

Abstract: Method and apparatus for signal reflection removal, such as echo cancellation, is described. Signal samples are delayed. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a communication network, such as in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. Echo cancellers described herein can be implemented in an FPGA. Echo in over a thousand channels can be cancelled using an FPGA and an external memory device. In embodiments for reflected signal cancellation, multiple stages of echo estimation are used.