Patents by Inventor Neil W. Songer
Neil W. Songer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10761579Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: GrantFiled: August 4, 2017Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Patent number: 10678199Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.Type: GrantFiled: June 23, 2016Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Barnes Cooper, Neil W. Songer
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Patent number: 10182398Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.Type: GrantFiled: March 8, 2017Date of Patent: January 15, 2019Assignee: Intel CorporationInventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
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Patent number: 10146290Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.Type: GrantFiled: July 24, 2017Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Seh W. Kwa, Neil W. Songer, Rob Gough, David J. Harriman
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Publication number: 20180088652Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.Type: ApplicationFiled: July 24, 2017Publication date: March 29, 2018Applicant: Intel CorporationInventors: Seh W. Kwa, Neil W. Songer, Rob Gough, David J. Harriman
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Patent number: 9874922Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.Type: GrantFiled: February 17, 2015Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, James G. Hermerding, II
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Publication number: 20170371402Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.Type: ApplicationFiled: June 23, 2016Publication date: December 28, 2017Applicant: INTEL CORPORATIONInventors: Barnes Cooper, Neil W. Songer
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Patent number: 9838967Abstract: An apparatus is provided that includes a transceiver to transmit and receive data between an upstream device and the apparatus, and further includes service latency reporting logic coupled to the transceiver to provide a service latency tolerance value of the apparatus to the upstream device, the service latency tolerance value corresponding to an activity state of the apparatus. The service latency tolerance value for an idle activity state can be greater than the service latency tolerance value for an active activity state.Type: GrantFiled: January 12, 2015Date of Patent: December 5, 2017Assignee: Intel CorporationInventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
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Publication number: 20170329377Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: ApplicationFiled: August 4, 2017Publication date: November 16, 2017Inventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Patent number: 9766673Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: GrantFiled: February 27, 2015Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Publication number: 20170177539Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Applicant: Intel CorporationInventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
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Patent number: 9541983Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.Type: GrantFiled: October 22, 2015Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Barnes Cooper, Jeffrey R Wilcox, Michael N Derr, Neil W Songer, Craig S Forbell
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Patent number: 9459684Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.Type: GrantFiled: December 10, 2013Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Robert E. Gough, Seh W. Kwa, Neil W. Songer, Jaya L. Jeyaseelan, Barnes Cooper
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Publication number: 20160252942Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: ApplicationFiled: February 27, 2015Publication date: September 1, 2016Inventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Publication number: 20160239068Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.Type: ApplicationFiled: February 17, 2015Publication date: August 18, 2016Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, VASUDEVAN SRINIVASAN, EUGENE GORBATOV, ANDREW D. HENROID, BARNES COOPER, DAVID W. BROWNING, GUY M. THERIEN, NEIL W. SONGER, JAMES G. HERMERDING, II
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Publication number: 20160041595Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Barnes Cooper, Jeffrey R. Wilcox, Michael N. Derr, Neil W. Songer, Craig S. Forbell
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Patent number: 9195292Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.Type: GrantFiled: June 26, 2013Date of Patent: November 24, 2015Assignee: Intel CorporationInventors: Barnes Cooper, Jeffrey R Wilcox, Michael N Derr, Neil W Songer, Craig S Forbell
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Publication number: 20150257101Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.Type: ApplicationFiled: January 12, 2015Publication date: September 10, 2015Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
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Publication number: 20150006923Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.Type: ApplicationFiled: June 26, 2013Publication date: January 1, 2015Inventors: Barnes Cooper, Jeffrey R. Wilcox, Michael N. Derr, Neil W. Songer, Craig S. Forbell
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Publication number: 20140101470Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Inventors: Robert E. GOUGH, Seh W. KWA, Neil W. SONGER, Jaya L. JEYASEELAN, Barnes COOPER