Patents by Inventor Nelson Mimura GONZALEZ
Nelson Mimura GONZALEZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11714615Abstract: Described are techniques for application migration. The techniques include migrating an application to a target cloud infrastructure and generating a cost-aware code dependency graph during execution of the application on the target cloud infrastructure. The techniques further include modifying the application by removing source code corresponding to unused nodes according to the cost-aware code dependency graph and replacing identified source code of a high-cost subgraph of the cost-aware code dependency graph with calls to a generated microservice configured to provide functionality similar to the identified source code. The techniques further include implementing the modified application on one or more virtual machines of the target cloud infrastructure.Type: GrantFiled: September 18, 2020Date of Patent: August 1, 2023Assignee: International Business Machines CorporationInventors: Bruno Silva, Marco Aurelio Stelmar Netto, Renato Luiz de Freitas Cunha, Nelson Mimura Gonzalez
-
Patent number: 11665087Abstract: A computer-implemented method, a computer program product, and a computer system for multi-path networking with a feature of multiplexing. One or more computing devices or servers configure wrappers for respective ones of applications and run the applications with the wrappers preloaded to the respective ones of the applications. The wrappers establish communication through one or more alternative paths between wrapped applications, where the one or more alternative paths are parallel to an original path between the applications. The wrappers exchange data between the applications through either the one or more alternative paths or the original path. The wrappers finalize connections through the one or more alternative paths, in response to all the data being exchanged.Type: GrantFiled: September 15, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Nelson Mimura Gonzalez, Tonia Elengikal, Guojing Cong
-
Publication number: 20230079088Abstract: A computer-implemented method, a computer program product, and a computer system for multi-path networking with a feature of multiplexing. One or more computing devices or servers configure wrappers for respective ones of applications and run the applications with the wrappers preloaded to the respective ones of the applications. The wrappers establish communication through one or more alternative paths between wrapped applications, where the one or more alternative paths are parallel to an original path between the applications. The wrappers exchange data between the applications through either the one or more alternative paths or the original path. The wrappers finalize connections through the one or more alternative paths, in response to all the data being exchanged.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Inventors: Nelson Mimura Gonzalez, Tonia Elengikal, Guojing Cong
-
Publication number: 20220206786Abstract: An embodiment includes executing a querying process that searches for candidate code libraries to replace a current library in a software application. The embodiment also includes receiving a search result from the querying process, wherein the search result includes a set of candidate code libraries. The embodiment also includes identifying a top candidate code library as a highest ranking code library of the set of candidate code libraries based on predetermined metrics. The embodiment also includes generating a revised software application from the original software application, the generating comprising replacing the current library in the original software application with the top candidate code library.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Applicant: International Business Machines CorporationInventors: Bruno Silva, Marco Aurelio Stelmar Netto, Renato Luiz de Freitas Cunha, Nelson Mimura Gonzalez
-
Publication number: 20220091829Abstract: Described are techniques for application migration. The techniques include migrating an application to a target cloud infrastructure and generating a cost-aware code dependency graph during execution of the application on the target cloud infrastructure. The techniques further include modifying the application by removing source code corresponding to unused nodes according to the cost-aware code dependency graph and replacing identified source code of a high-cost subgraph of the cost-aware code dependency graph with calls to a generated microservice configured to provide functionality similar to the identified source code. The techniques further include implementing the modified application on one or more virtual machines of the target cloud infrastructure.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Bruno Silva, Marco Aurelio Stelmar Netto, Renato Luiz de Freitas Cunha, Nelson Mimura Gonzalez
-
Patent number: 11163592Abstract: A benchmark generating system is presented. The system monitors an execution of a computer program to collect performance traces for one or more load metrics. The system generates a program model based on the collected performance traces. Each state of the program model corresponds to a workload level at one load metric or a combination of workload levels at the two or more load metrics. The system also generates one or more workload models based on the collected performance traces. Each workload model is configured to generate simulated workload for one load metric of the one or more load metrics at a workload level that is determined based on a state of the program model. The system provides the generated program model and the generated workload models as a benchmark of the computer program.Type: GrantFiled: January 10, 2020Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruno Silva, Renato Luiz de Freitas Cunha, Nelson Mimura Gonzalez, Marco Aurelio Stelmar Netto
-
Publication number: 20210216338Abstract: A benchmark generating system is presented. The system monitors an execution of a computer program to collect performance traces for one or more load metrics. The system generates a program model based on the collected performance traces. Each state of the program model corresponds to a workload level at one load metric or a combination of workload levels at the two or more load metrics. The system also generates one or more workload models based on the collected performance traces. Each workload model is configured to generate simulated workload for one load metric of the one or more load metrics at a workload level that is determined based on a state of the program model. The system provides the generated program model and the generated workload models as a benchmark of the computer program.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: Bruno Silva, Renato Luiz de Freitas Cunha, Nelson Mimura Gonzalez, Marco Aurelio Stelmar Netto
-
Patent number: 10719903Abstract: Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.Type: GrantFiled: December 22, 2017Date of Patent: July 21, 2020Assignee: International Business Machines CorporationInventors: Fausto Artico, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
-
Patent number: 10540737Abstract: Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.Type: GrantFiled: December 22, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Fausto Artico, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
-
Publication number: 20190197653Abstract: Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Fausto ARTICO, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
-
Publication number: 20190197652Abstract: Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Fausto ARTICO, Jose R. BRUNHEROTO, Juan Gonzalez GARCIA, Nelson Mimura GONZALEZ