Patents by Inventor Nenad Miladinovic
Nenad Miladinovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143439Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.Type: ApplicationFiled: November 22, 2022Publication date: May 2, 2024Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
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Patent number: 11740802Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.Type: GrantFiled: July 29, 2021Date of Patent: August 29, 2023Assignee: PURE STORAGE, INC.Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
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Publication number: 20230267040Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.Type: ApplicationFiled: May 1, 2023Publication date: August 24, 2023Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
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Publication number: 20230251944Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
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Patent number: 11656939Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.Type: GrantFiled: November 24, 2021Date of Patent: May 23, 2023Assignee: PURE STORAGE, INC.Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Patent number: 11620197Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.Type: GrantFiled: August 2, 2021Date of Patent: April 4, 2023Assignee: PURE STORAGE, INC.Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Publication number: 20230089583Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.Type: ApplicationFiled: November 18, 2022Publication date: March 23, 2023Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
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Patent number: 11544143Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.Type: GrantFiled: March 26, 2021Date of Patent: January 3, 2023Assignee: Pure Storage, Inc.Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
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Publication number: 20220404970Abstract: A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.Type: ApplicationFiled: August 26, 2022Publication date: December 22, 2022Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Patent number: 11449232Abstract: A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.Type: GrantFiled: October 27, 2016Date of Patent: September 20, 2022Assignee: Pure Storage, Inc.Inventors: Hari Kannan, Nenad Miladinovic, Randy Zhao
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Patent number: 11442625Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.Type: GrantFiled: March 26, 2021Date of Patent: September 13, 2022Assignee: Pure Storage, Inc.Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Patent number: 11416338Abstract: A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.Type: GrantFiled: April 24, 2020Date of Patent: August 16, 2022Assignee: Pure Storage, Inc.Inventors: Hari Kannan, Nenad Miladinovic
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Publication number: 20220083420Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.Type: ApplicationFiled: November 24, 2021Publication date: March 17, 2022Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Patent number: 11204830Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.Type: GrantFiled: February 25, 2020Date of Patent: December 21, 2021Assignee: Pure Storage, Inc.Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Publication number: 20210365337Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.Type: ApplicationFiled: August 2, 2021Publication date: November 25, 2021Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Publication number: 20210357133Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.Type: ApplicationFiled: July 29, 2021Publication date: November 18, 2021Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
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Publication number: 20210334157Abstract: A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Inventors: Hari Kannan, Nenad Miladinovic
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Patent number: 11099749Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.Type: GrantFiled: October 22, 2018Date of Patent: August 24, 2021Assignee: Pure Storage, Inc.Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
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Patent number: 11080154Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.Type: GrantFiled: May 24, 2019Date of Patent: August 3, 2021Assignee: Pure Storage, Inc.Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
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Publication number: 20210232323Abstract: A system operates solid-state storage memory. The system determines that a portion of the solid-state storage memory is of a type that has a failure mode of threshold voltage shift over time from successive reads at time intervals. The system alters or turns off a background process that performs such successive reads to check for memory reliability, for at least the portion of the solid-state storage memory. Or, the system uses the portion of solid-state storage memory for data bits, not parity bits.Type: ApplicationFiled: April 16, 2021Publication date: July 29, 2021Inventors: Hari Kannan, Nenad Miladinovic, Eric Michael Verwillow, Davis Yeung