Patents by Inventor Nestor A. Bojarczuk, Jr.
Nestor A. Bojarczuk, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8193051Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: GrantFiled: March 14, 2011Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20110165767Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nestor A. Bojarczuk, JR., Cyril Cabral, JR., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7928514Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: GrantFiled: January 16, 2009Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7745278Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.Type: GrantFiled: September 16, 2008Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20090152642Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: ApplicationFiled: January 16, 2009Publication date: June 18, 2009Applicant: International Business Machines CorporationInventors: Nestor A. Bojarczuk, JR., Cyril Cabral, JR., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7488640Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.Type: GrantFiled: October 29, 2004Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard Cartier, Supratik Guha, Lars-Ake Ragnarsson
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Patent number: 7479683Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: GrantFiled: October 1, 2004Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20090011610Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.Type: ApplicationFiled: September 16, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nestor A. Bojarczuk, JR., Cyril Cabral, JR., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7452767Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.Type: GrantFiled: August 7, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7446380Abstract: The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.Type: GrantFiled: April 29, 2005Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Michael P. Chudzik, Matthew W. Copel, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7242055Abstract: A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.Type: GrantFiled: November 15, 2004Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Paul C. Jamison, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7105889Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.Type: GrantFiled: June 4, 2004Date of Patent: September 12, 2006Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7078301Abstract: A data storage element (and method of forming the same) includes a substrate comprising a semiconductor material, a metal oxide layer including an electrically insulating rare earth metal oxide disposed upon a surface of the substrate, a conductive material disposed upon the metal oxide layer, a first electrode electrically connected to the conductive material, and a second electrode connected to the substrate.Type: GrantFiled: October 1, 2004Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard Albert Cartier, Supratik Guha
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Patent number: 6894338Abstract: A data storage element (and method of forming the same) includes a substrate comprising a semiconductor material, a metal oxide layer including an electrically insulating rare earth metal oxide disposed upon a surface of the substrate, a conductive material disposed upon the metal oxide layer, a first electrode electrically connected to the conductive material, and a second electrode connected to the substrate.Type: GrantFiled: January 11, 2002Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard Albert Cartier, Supratik Guha
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Patent number: 6861728Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.Type: GrantFiled: December 20, 2002Date of Patent: March 1, 2005Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard A. Cartier, Matthew W. Copel, Supratik Guha
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Patent number: 6831339Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.Type: GrantFiled: January 8, 2001Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard Cartier, Supratik Guha, Lars-Ake Ragnarsson
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Patent number: 6541079Abstract: A method of forming a layer of oxide or oxynitride upon a substrate including first placing a substrate having an upper surface and a lower surface in a high vacuum chamber and then exposing the upper surface to a beam of atoms or molecules, or both, of oxygen or nitrogen or a combination of same at a temperature sufficient to form a reacted layer on the upper surface of said substrate wherein said layer has a chemical composition different from the chemical composition of said substrate. The reacted upper layer is then exposed simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or metal molecules selected from the group consisting of Al, Si, Zr, La, Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer in said layer.Type: GrantFiled: October 25, 1999Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard A. Cartier, Supratik Guha
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Patent number: 6528374Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.Type: GrantFiled: February 5, 2001Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Eduard A. Cartier, Matthew W. Copel, Supratik Guha
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Patent number: 6333067Abstract: A method of forming the device, includes selective area deposition of a ferromagnetic material on a substrate. The substrate surface is partially covered with material having a crystal structure having at least one symmetry relation with the crystal structure of the ferromagnetic material.Type: GrantFiled: June 13, 2001Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Peter R. Duncombe, Supratik Guha, Arunava Gupta, Joseph M. Karasinski, Xinwei Li
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Patent number: 6299991Abstract: A device and a method of forming the device, includes selective area deposition of a ferromagnetic material on a substrate.Type: GrantFiled: October 15, 1998Date of Patent: October 9, 2001Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Peter R. Duncombe, Supratik Guha, Arunava Gupta, Joseph M. Karasinski, Xinwei Li