Patents by Inventor Neven Klacar
Neven Klacar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11029748Abstract: Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.Type: GrantFiled: March 15, 2016Date of Patent: June 8, 2021Assignee: QUALCOMM IncorporatedInventors: Neven Klacar, Muralidhar Krishnamoorthy, Hariharan Sukumar
-
Patent number: 10915490Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.Type: GrantFiled: February 7, 2019Date of Patent: February 9, 2021Assignee: QUALCOMM IncorporatedInventors: Neven Klacar, Murali Krishna, Arunn Coimbatore Krishnamurthy, Jitendra Prasad, Jean-Marie Quoc Danh Tran
-
Publication number: 20200008144Abstract: Link speed control systems for power optimization are disclosed. In one aspect, a communication link adjusts a data transfer speed based on link utilization levels. In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Neven Klacar, Murali Krishna, Shailesh Maheshwari, Suyash Ranjan, Ofer Rosenberg
-
Patent number: 10482050Abstract: Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.Type: GrantFiled: October 2, 2017Date of Patent: November 19, 2019Assignee: Qualcomm IncorporatedInventors: Neven Klacar, Yan He, Murali Krishna
-
Publication number: 20190251056Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.Type: ApplicationFiled: February 7, 2019Publication date: August 15, 2019Inventors: Neven Klacar, Murali Krishna, Arunn Coimbatore Krishnamurthy, Jitendra Prasad, Jean-Marie Quoc Danh Tran
-
Publication number: 20180129623Abstract: Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.Type: ApplicationFiled: October 2, 2017Publication date: May 10, 2018Inventors: Neven Klacar, Yan He, Murali Krishna
-
Publication number: 20170280385Abstract: Link speed control systems for power optimization are disclosed. In one aspect, a communication link adjusts a data transfer speed based on link utilization levels. In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.Type: ApplicationFiled: March 22, 2017Publication date: September 28, 2017Inventors: Neven Klacar, Murali Krishna, Shailesh Maheshwari, Suyash Ranjan, Ofer Rosenberg
-
Publication number: 20170269675Abstract: Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.Type: ApplicationFiled: March 15, 2016Publication date: September 21, 2017Inventors: Neven Klacar, Muralidhar Krishnamoorthy, Hariharan Sukumar
-
Patent number: 9535490Abstract: Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.Type: GrantFiled: December 12, 2014Date of Patent: January 3, 2017Assignee: QUALCOMM IncorporatedInventors: Vinod Harimohan Kaushik, Uppinder Singh Babbar, Andrei Danaila, Neven Klacar, Muralidhar Coimbatore Krishnamoorthy, Arunn Coimbatore Krishnamurthy, Vaibhav Kumar, Vanitha Aravamudhan Kumar, Shailesh Maheshwari, Alok Mitra, Roshan Thomas Pius, Hariharan Sukumar
-
Publication number: 20150169037Abstract: Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.Type: ApplicationFiled: December 12, 2014Publication date: June 18, 2015Inventors: Vinod Harimohan Kaushik, Uppinder Singh Babbar, Andrei Danaila, Neven Klacar, Muralidhar Coimbatore Krishnamoorthy, Arunn Coimbatore Krishnamurthy, Vaibhav Kumar, Vanitha Aravamudhan Kumar, Shailesh Maheshwari, Alok Mitra, Roshan Pius, Hariharan Sukumar
-
Patent number: RE49591Abstract: Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.Type: GrantFiled: July 28, 2021Date of Patent: July 25, 2023Assignee: QUALCOMM IncorporatedInventors: Vinod Harimohan Kaushik, Uppinder Singh Babbar, Andrei Danaila, Neven Klacar, Muralidhar Coimbatore Krishnamoorthy, Arunn Coimbatore Krishnamurthy, Vaibhav Kumar, Vanitha Aravamudhan Kumar, Shailesh Maheshwari, Alok Mitra, Roshan Thomas Pius, Hariharan Sukumar
-
Patent number: RE49652Abstract: Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.Type: GrantFiled: April 26, 2021Date of Patent: September 12, 2023Assignee: QUALCOMM IncorporatedInventors: Vinod Harimohan Kaushik, Uppinder Singh Babbar, Andrei Danaila, Neven Klacar, Muralidhar Coimbatore Krishnamoorthy, Arunn Coimbatore Krishnamurthy, Vaibhav Kumar, Vanitha Aravamudhan Kumar, Shailesh Maheshwari, Alok Mitra, Roshan Thomas Pius, Hariharan Sukumar