Patents by Inventor Newell E. Chiesl

Newell E. Chiesl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6775630
    Abstract: The present invention is directed to a system and method for providing access to semiconductor manufacturing information. The present invention system and method allows users to interface with semiconductor characteristic data and to data associated with manufacturing conditions over a network. The system includes at least one input device for entering manufacturing data. A data storage device capable of storing the database of manufacturing data, including semiconductor characteristic data and manufacturing conditions is networked to the at least one input device. A plurality of remote devices suitable for interfacing with the data are networked to the storage device, such that the manufacturing data is provided to a website for access upon occurrence of failure event.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Nima A. Behkami, James W. Seale, Newell E. Chiesl, Mark A. Giewont, Robert B. Powell
  • Patent number: 6770505
    Abstract: An arrangement for measuring pressure on a semiconductor wafer and an associated method for fabricating a semiconductor wafer are disclosed.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventor: Newell E. Chiesl
  • Patent number: 6716364
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Patent number: 6641635
    Abstract: An air filtration system uses a liquid to remove impurities from the air. A specialized chamber allows the air and liquid to contact each other in close proximity, so that the liquid can pick up not only particulate matter, but fumes and toxic gasses as well. The air can be bubbled through the liquid, or the liquid can be introduced into the chamber as a gentle rain, a spray, a vapor, a waterfall, or any other configuration that allows active contact between the two mediums. The liquid can then be cleaned of contaminants, e.g., by centrifugal force, while the liquid is then reused.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: November 4, 2003
    Assignee: LSI Logic Corporation
    Inventor: Newell E. Chiesl
  • Patent number: 6582568
    Abstract: The present invention concerns an apparatus comprising a fixture and a sputtering device. The fixture may be configured to position a semiconductor wafer in a plasma. The sputtering device may be configured to sputter metal atoms onto a surface of the wafer in a direction perpendicular to the surface.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: June 24, 2003
    Assignee: LSI Logic Corporation
    Inventor: Newell E. Chiesl
  • Publication number: 20020196969
    Abstract: The present invention is directed to a system and method for providing access to semiconductor manufacturing information. The present invention system and method allows users to interface with semiconductor characteristic data and to data associated with manufacturing conditions over a network. The system includes at least one input device for entering manufacturing data. A data storage device capable of storing the database of manufacturing data, including semiconductor characteristic data and manufacturing conditions is networked to the at least one input device. A plurality of remote devices suitable for interfacing with the data are networked to the storage device, such that the manufacturing data is provided to a website for access upon occurrence of failure event.
    Type: Application
    Filed: April 23, 2002
    Publication date: December 26, 2002
    Inventors: Nima A. Behkami, James W. Seale, Newell E. Chiesl, Mark A. Giewont, Robert B. Powell
  • Patent number: 6375791
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 23, 2002
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Patent number: 6177305
    Abstract: Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: January 23, 2001
    Assignee: LSI Logic Corporation
    Inventors: Verne C. Hornback, Derryl D. J. Allman, Newell E. Chiesl