Abstract: An amplifier system includes an amplifier transistor and a reference transistor used to provide a direct current (DC) bias voltage to bias a gate terminal of the amplifier transistor. The amplifier transistor may have a drain terminal coupled to a drain voltage supply and a radio frequency (RF) output node and a gate terminal coupled to bias circuitry that includes the reference transistor. The reference transistor may have a gate terminal coupled to a reference potential, a drain terminal coupled to the drain voltage supply, and a source terminal coupled to a constant current source and to the gate terminal of the amplifier transistor. The reference transistor may be formed on the same die as the amplifier transistor and may have a threshold voltage that is correlated with that of the amplifier transistor.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a bias controller for an amplifier circuit involves obtaining temperature data corresponding to a temperature of the amplifier circuit, generating a proportional to absolute temperature (PTAT) bias voltage based on a first PTAT slope when the temperature is within a first range of temperatures or a second PTAT slope when the temperature is within a second range of temperatures, wherein the second PTAT slope is greater than the first PTAT slope, and biasing the amplifier circuit based on the generated PTAT bias voltage.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a bias controller for an amplifier circuit involves obtaining temperature data corresponding to a temperature of the amplifier circuit, generating a proportional to absolute temperature (PTAT) bias voltage based on a first PTAT slope when the temperature is within a first range of temperatures or a second PTAT slope when the temperature is within a second range of temperatures, wherein the second PTAT slope is greater than the first PTAT slope, and biasing the amplifier circuit based on the generated PTAT bias voltage.

Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.

Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.

Abstract: Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608).

Abstract: A circuit for protecting an electronic device including a differential nulling avalanche clamp circuit (200, 300) and method of using the circuit in an electronic system (100) to limit radio frequency overdrive. The electronic system (100) includes a surge clamp (130) coupled to dissipate an electrical surge effect of a first frequency from a noise sensitive node (140) and a ring wave clamp (120) coupled to dissipate an electrical surge effect of a second frequency from the noise sensitive node (140). The ring wave clamp circuit (200, 300) includes a first bipolar junction transistor (210, 310), a second bipolar junction transistor (220, 320) coupled to the first bipolar junction transistor (210, 310), and a resistive circuit (230, 330, 340) coupled to the first and second bipolar junction transistors (210, 220, 310, 320).

Abstract: A wide bandwidth linear amplifier (10) that has an operating band in excess of 1 GHz mounts the high power dissipating components (11) of the amplifier (10), and the components 917, 18) that control the high frequency gain and stability of the amplifier (10) onto a daughter board (32) that has a high thermal conductivity. The daughter board (32) and the remaining circuit components (21, 22, 23, 24, 26a, 26b) are then mounted on a mother board (31) that has a lower thermal conductivity. The assembly (30) reduces the circuit's parasitic inductance (46, 47, 48, 49) and parasitic capacitance (51, 52), and provides unconditional stability at high frequencies.