Abstract: A computer system is provided that has a main memory and a plurality of processor agents each having a last level cache and a hot cache. Each processor agent is configured to store cache lines in the last level cache and the hot cache. The hot cache is configured to store cache lines in the hot coherency state. Cache lines in the hot coherency state are cache lines that have been read and modified. The hot cache is smaller in size than the last level cache to facilitate fast access to the cache lines in the hot coherency state in response to a future request to read with intent to modify. A bus connects each of the plurality of processor agents to the main memory.

Abstract: A method for cache management is disclosed. The method can assign or determined identifiers for lines of binary code that are, or will be stored in cache. The method can create a cache directory that utilizes the identifier to keep an eviction count and/or a reload count for cached lines. Thus, each time a line is entered into, or evicted from cache, the cache eviction log can be amended accordingly. When a processor receives or creates an instruction that requests that a line be evicted from cache, a cache manager log can identify a line, or lines of binary code to be evicted based on data by accessing the cache directory and then the line(s) can be evicted.

Abstract: The invention is directed to the identifying, tracking, and storing of hot cache lines in an SMP environment. A method in accordance with an embodiment of the present invention includes: accessing, by a first processor, a cache line from main memory; modifying and storing the cache line in the L2 cache of the first processor; requesting, by a second processor, the cache line; identifying, by the first processor, that the cache line stored in the L2 cache of the first processor has previously been modified; marking, by the first processor, the cache line as a hot cache line; forwarding the hot cache line to the second processor; modifying, by the second processor, the hot cache line; and storing the hot cache line in the hot cache of the second processor.

Abstract: Administering an access conflict in a computer memory cache, including receiving in a memory cache controller a write address and write data from a store memory instruction execution unit of a superscalar computer processor and a read address for read data from a load memory instruction execution unit of the superscalar computer processor, for the write data to be written to and the read data to be read from a same cache line in the computer memory cache simultaneously on a current clock cycle; storing by the memory cache controller the write data in the same cache line on the current clock cycle; stalling, by the memory cache controller in the load memory instruction execution unit, a corresponding load microinstruction; and reading by the memory cache controller from the computer memory cache on a subsequent clock cycle read data from the read address.

Abstract: Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.