Patents by Inventor Niall Fitzgerald

Niall Fitzgerald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966477
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for generic process chain entity mapping. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to receive process chain input data, the input data including a system path, identify a match between a path alias and the input data, wherein the path alias includes an alias for one or more system path format patterns, extract at least one of (1) metadata information or (2) command line parameter information from the match, and output transformed data based on the at least one of the extracted metadata information or command line parameter information, the transformed data output in a generalized format.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 23, 2024
    Assignee: MUSARUBRA US LLC
    Inventors: Niall Fitzgerald, Jonathan King, Christiaan Beek
  • Patent number: 11931261
    Abstract: A prolapse prevention device formed by a continuous wire-like structure having a first end and a second end disconnected from each other. The continuous wire-like structure of the prolapse prevention device is substantially straight in a delivery configuration. The prolapse prevention device in a deployed configuration includes a centering ring of the continuous wire-like structure configured to seat adjacent to and upstream of an annulus of a heart valve in situ, a vertical support of the continuous wire-like structure which extends from the centering ring and includes an apex configured to seat against a roof of an atrium in situ, and a leaflet backstop of the continuous wire-like structure extending radially inward from the centering ring and configured to contact at least at least a first leaflet of the heart valve in situ to exert a pressure in a downstream direction on the first leaflet to prevent the first leaflet from prolapsing into the atrium.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: March 19, 2024
    Assignee: MEDTRONIC VASCULAR, INC.
    Inventors: Niall Duffy, David Farascioni, Adam Fitzgerald, Nathan Knutson, Ana Menk, Aran Murray, Jay Rassat
  • Publication number: 20230222220
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for generic process chain entity mapping. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to receive process chain input data, the input data including a system path, identify a match between a path alias and the input data, wherein the path alias includes an alias for one or more system path format patterns, extract at least one of (1) metadata information or (2) command line parameter information from the match, and output transformed data based on the at least one of the extracted metadata information or command line parameter information, the transformed data output in a generalized format.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Niall Fitzgerald, Jonathan King, Christiaan Beek
  • Publication number: 20230208872
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine mutex entropy for malware classification. An example apparatus includes interface circuitry to access a mutex associated with a software application, the mutex to include a mutex identifier string, normalizer circuitry to normalize the mutex identifier string, character probability circuitry to determine character probabilities of characters within the normalized mutex identifier string, the character probabilities based on a historical mutex character distribution, entropy calculator circuitry to calculate an entropy value for the mutex based on the character probabilities, classifier circuitry to classify the mutex as clean or malicious based on the entropy value, and protector circuitry to mitigate malicious attacks based on the classification.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Niall Fitzgerald, German Lancioni, Brian Gaither
  • Patent number: 11669615
    Abstract: There is disclosed in one example a computer-implemented method of detecting a statistically-significant security event and automating a response thereto, including: querying, or causing to be queried, a security intelligence database for sector-wise historical norms for an indicator of compromise (IoC); obtaining sector-wise expected prevalence data for the IoC; receiving observed sector-wise prevalence data for the IoC; computing a first test statistic from a goodness-of-fit test between the observed and expected prevalences; from the observed sector-wise prevalence data, computing a second test statistic from a difference between a highest prevalence and a next-highest prevalence; computing a third test statistic from a difference between the observed prevalence of a highest prevalence sector and the expected prevalence for the highest prevalence sector; selecting a least significant statistic from among the first, second, and third test statistics; and determining from the least significant statistic whet
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: June 6, 2023
    Assignee: McAfee, LLC
    Inventors: Niall Fitzgerald, Steven Grobman, Jonathan B. King, Sorcha Bairbre Healy, Gerard Donal Murphy
  • Publication number: 20220216978
    Abstract: Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.
    Type: Application
    Filed: May 15, 2020
    Publication date: July 7, 2022
    Inventor: Niall Fitzgerald
  • Publication number: 20220116408
    Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform including a processor circuit and a memory circuit; first means for accessing a machine learning engine; second means for accessing a user interface; and instructions encoded within the memory to instruct the processor to: load into the machine learning engine via the first means an object prevalence model, including an enterprise-specific prevalence model; provide to the machine learning engine an object set from the enterprise; identify an enterprise-novel object from the object set; solicit and receive via the second means user-sourced feedback for the enterprise-novel object; and act according to the user-sourced feedback.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Applicant: McAfee, LLC
    Inventors: Sorcha Bairbre Healy, Gerard Donal Murphy, Steven Grobman, Niall Fitzgerald, Jillian Anne Daly, Sandeep Thakur, Brian Gaither, Niamh Minihane, Catherine Costigan
  • Publication number: 20220027463
    Abstract: There is disclosed in one example a computer-implemented method of detecting a statistically-significant security event and automating a response thereto, including: querying, or causing to be queried, a security intelligence database for sector-wise historical norms for an indicator of compromise (IoC); obtaining sector-wise expected prevalence data for the IoC; receiving observed sector-wise prevalence data for the IoC; computing a first test statistic from a goodness-of-fit test between the observed and expected prevalences; from the observed sector-wise prevalence data, computing a second test statistic from a difference between a highest prevalence and a next-highest prevalence; computing a third test statistic from a difference between the observed prevalence of a highest prevalence sector and the expected prevalence for the highest prevalence sector; selecting a least significant statistic from among the first, second, and third test statistics; and determining from the least significant statistic whet
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Applicant: McAfee, LLC
    Inventors: Niall Fitzgerald, Steven Grobman, Jonathan B. King, Sorcha Bairbre Healy, Gerard Donal Murphy
  • Patent number: 10785069
    Abstract: This disclosure describes techniques for detecting link loss in a physical layer receiver of a communication system. The system includes a slicer coupled to receive, at a slicer input, a signal from a channel equalizer and map the signal to a physical coding sublayer (PCS) level at a slicer output and processor coupled to at least one of the slicer input or the slicer output. The processor is configured to analyze a window of consecutive samples at the at least one of the slicer input or the slicer output over a time window; increment a counter as a function of the window of consecutive samples at the at least one of the slicer input or the slicer output; compare the counter to a threshold; and generate a signal indicating link loss in response to determining that the counter corresponds to the threshold independently of a timer.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 22, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Niall Fitzgerald, Oisín Ó Cuanacháin
  • Publication number: 20200186396
    Abstract: This disclosure describes techniques for detecting link loss in a physical layer receiver of a communication system. The system includes a slicer coupled to receive, at a slicer input, a signal from a channel equalizer and map the signal to a physical coding sublayer (PCS) level at a slicer output and processor coupled to at least one of the slicer input or the slicer output. The processor is configured to analyze a window of consecutive samples at the at least one of the slicer input or the slicer output over a time window; increment a counter as a function of the window of consecutive samples at the at least one of the slicer input or the slicer output; compare the counter to a threshold; and generate a signal indicating link loss in response to determining that the counter corresponds to the threshold independently of a timer.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 11, 2020
    Inventors: Niall Fitzgerald, Oisín Ó. Cuanacháin
  • Patent number: 9197460
    Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 24, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Vladimir Sindalovsky, Lane A. Smith, Niall Fitzgerald
  • Publication number: 20150319018
    Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.
    Type: Application
    Filed: May 28, 2014
    Publication date: November 5, 2015
    Applicant: LSI Corporation
    Inventors: Vladimir Sindalovsky, Lane A. Smith, Niall Fitzgerald