Patents by Inventor Niang-Chu CHEN
Niang-Chu CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11775178Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.Type: GrantFiled: June 23, 2021Date of Patent: October 3, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jun Tao, Niang-Chu Chen
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Patent number: 11606105Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: GrantFiled: November 17, 2021Date of Patent: March 14, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jun Tao, Niang-Chu Chen
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Patent number: 11557352Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.Type: GrantFiled: April 29, 2021Date of Patent: January 17, 2023Assignee: Western Digital Technologies, Inc.Inventors: Niang-Chu Chen, Jun Tao
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Patent number: 11531587Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.Type: GrantFiled: June 24, 2021Date of Patent: December 20, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
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Publication number: 20220077876Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Jun TAO, Niang-Chu CHEN
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Patent number: 11211949Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: GrantFiled: March 19, 2020Date of Patent: December 28, 2021Assignee: Western Digital Technologies, Inc.Inventors: Jun Tao, Niang-Chu Chen
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Publication number: 20210318930Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Jun TAO, Niang-Chu CHEN, Mark Joseph DANCHO, Xiaoheng CHEN
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Publication number: 20210318810Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Jun TAO, Niang-Chu CHEN
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Patent number: 11093326Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.Type: GrantFiled: January 23, 2020Date of Patent: August 17, 2021Assignee: Western Digital Technologies, Inc.Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
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Publication number: 20210249088Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Inventors: Niang-Chu CHEN, Jun TAO
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Patent number: 11086529Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.Type: GrantFiled: September 26, 2018Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: Jun Tao, Niang-Chu Chen
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Patent number: 11017867Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.Type: GrantFiled: March 19, 2020Date of Patent: May 25, 2021Assignee: Western Digital Technologies, Inc.Inventors: Niang-Chu Chen, Jun Tao
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Patent number: 10747454Abstract: Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.Type: GrantFiled: January 28, 2019Date of Patent: August 18, 2020Assignee: Western Digital Technologies, Inc.Inventors: Niang-Chu Chen, Jun Tao
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Publication number: 20200257463Abstract: Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Niang-Chu CHEN, Jun TAO
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Publication number: 20200241776Abstract: Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Niang-Chu CHEN, Jun TAO
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Publication number: 20200220562Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Jun TAO, Niang-Chu CHEN
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Publication number: 20200219571Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Niang-Chu CHEN, Jun TAO
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Publication number: 20200159620Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.Type: ApplicationFiled: January 23, 2020Publication date: May 21, 2020Inventors: Jun TAO, Niang-Chu CHEN, Mark Joseph DANCHO, Xiaoheng CHEN
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Patent number: 10636495Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.Type: GrantFiled: August 1, 2018Date of Patent: April 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Niang-Chu Chen, Jun Tao
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Patent number: 10637511Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: GrantFiled: December 18, 2017Date of Patent: April 28, 2020Assignee: Western Digital Technologies, IncInventors: Jun Tao, Niang-Chu Chen