Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: An example operation may include one or more of identifying a current tool configuration used by a tool device to construct semiconductor devices, retrieving a smart contract stored in a blockchain to identify whether an updated tool configuration exists, responsive to identifying the updated tool configuration, transmitting an update that includes the updated tool configuration to the tool device, and responsive to receiving the updated tool configuration at the tool device, initiating construction of the semiconductor devices.

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.

Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.

Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: An example operation may include one or more of identifying a current tool configuration used by a tool device to construct semiconductor devices, retrieving a smart contract stored in a blockchain to identify whether an updated tool configuration exists, responsive to identifying the updated tool configuration, transmitting an update that includes the updated tool configuration to the tool device, and responsive to receiving the updated tool configuration at the tool device, initiating construction of the semiconductor devices.

Abstract: A method includes forming a memory element on a first metal layer. A first cap layer is formed on the first metal layer and sidewalls of the memory element. A first dielectric layer is formed on the first cap layer and a portion of the cap layer on sidewalls of the memory element. A second metal layer is formed on the first dielectric layer. A portion of the memory element is removed and forms an opening. A second cap layer is formed on the top surface of the second metal layer. A second dielectric layer is deposited on the second cap layer and filling the opening. A via is etched in the second dielectric layer exposing a top surface of the memory element. A third metal layer is deposited on the second dielectric layer and filling the via.

Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein a portion of the intervening metallization level (MX+1) is in a pathway of the skip via.