Abstract: Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) comprising a first source/drain (S/D), a second FET comprising a second S/D squarely above the first S/D, and a shared S/D contact. The shared S/D may include a recessed portion between the first S/D and the second S/D, a side portion above the recessed portion, and a top portion above the second S/D. The side portion may contact a lateral side of the second S/D.

Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: A semiconductor device includes a frontside including first metal structures, transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure and a power circuit on the backside and connected to the transistors by backside contacts. A backside dielectric isolation has a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors.

Abstract: A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.