Patents by Inventor Nicholas CALLEGARI

Nicholas CALLEGARI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic yield prediction
    Patent number: 9470743
    Abstract: Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 18, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Nicholas Callegari, Bruce Cory, Joe Greco
  • DYNAMIC YIELD PREDICTION
    Publication number: 20150253373
    Abstract: Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Applicant: NVIDIA Corporation
    Inventors: Nicholas CALLEGARI, Bruce CORY, Joe GRECO
  • System and method for reducing the generation of inconsequential violations resulting from timing analyses
    Patent number: 7971169
    Abstract: A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation identifier configured to identify at least some timing violations in a circuit based on a timing analysis, (2) an unsensitizable path identifier configured to identify at least some unsensitizable paths in the circuit and (3) a repair list generator coupled to the timing violation identifier and the unsensitizable path identifier and configured to generate a repair list based on both the at least some timing violations and the at least some unsensitizable paths.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: June 28, 2011
    Assignee: LSI Corporation
    Inventors: Alexander Y. Tetelbaum, Sreejit Chakravarty, Nicholas A. Callegari