Patents by Inventor Nicholas Eib

Nicholas Eib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7634389
    Abstract: A method for obtaining an optimal reflectivity value for complex multilayer stacks is disclosed. Aspects of the present invention include generating a model of a multilayer stack and parameterizing each layer by a thickness and an index of refraction; allowing a user to input values for the parameters; calculating an extrema for a cost function of reflectivity R using the input parameter values; calculating sensitivity values S for the extrema points; and obtaining an optimal value by calculating a cost function R+S.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: December 15, 2009
    Assignee: LSI Corporation
    Inventors: Lav Ivanovic, Nicholas Eib, Xudong Xu
  • Patent number: 7313508
    Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
  • Publication number: 20070247604
    Abstract: The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.
    Type: Application
    Filed: June 27, 2007
    Publication date: October 25, 2007
    Inventors: Nicholas Eib, Ebo Croffie, Neal Callan
  • Publication number: 20060203220
    Abstract: The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the position and tilt of the individually controllable elements can be achieved by two electrodes operable over a range of values.
    Type: Application
    Filed: October 19, 2005
    Publication date: September 14, 2006
    Applicants: ASML Netherlands B.V., ASML Holding N.V., LSI Logic Corporation
    Inventors: Kars Troost, Johannes Baselmans, Arno Bleeker, Louis Markoya, Neal Callan, Nicholas Eib
  • Publication number: 20050275814
    Abstract: The present invention provides methods and apparatus for accomplishing a optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Application
    Filed: December 14, 2004
    Publication date: December 15, 2005
    Inventors: Nicholas Eib, Ebo Croffie, Neal Callan
  • Publication number: 20050237508
    Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a off axis light to reduce the effect of zero order light to improve the process window for maskless phase shift lithography systems and methodologies. A lithography system is provided. The lithography system provided uses off axis light beams projected onto a mirror array configured to generate a phase shift optical image pattern. This pattern is projected onto a photoimageable layer formed on the target substrate to facilitate pattern transfer.
    Type: Application
    Filed: December 14, 2004
    Publication date: October 27, 2005
    Inventors: Nicholas Eib, Ebo Croffie, Neal Callan
  • Publication number: 20050196681
    Abstract: A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 8, 2005
    Inventors: Ebo Croffle, Nicholas Eib, Mario Garza, Paul Filseth, Lav Ivanovic
  • Publication number: 20050151949
    Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a blocker to block zero order light to improve image quality for phase shift lithography systems and methodologies. A maskless lithography system is provided. The lithography system provided uses a phase shift pattern generator which projects a phase shift image pattern along an optical path onto a photoimageable layer of a substrate in order to facilitate pattern transfer. A blocking element is interposed in the optical path to block zero order light in the image pattern, thereby improving image quality.
    Type: Application
    Filed: November 12, 2004
    Publication date: July 14, 2005
    Inventors: Nicholas Eib, Ebo Croffie, Christopher Neville, Neal Callan
  • Publication number: 20050153246
    Abstract: The present invention provides methods and apparatus for accomplishing a strong phase shift direct write lithography process using reconfigurable optical mirrors. A maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used to generate strong phase shift optical patterns which are directed onto a photoimageable layer of a substrate in order to facilitate pattern transfer. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement.
    Type: Application
    Filed: November 19, 2004
    Publication date: July 14, 2005
    Inventors: Nicholas Eib, Ebo Croffle, Neal Callan
  • Publication number: 20050114094
    Abstract: A method for obtaining an optimal reflectivity value for complex multilayer stacks is disclosed. Aspects of the present invention include generating a model of a multilayer stack and parameterizing each layer by a thickness and an index of refraction; allowing a user to input values for the parameters; calculating an extrema for a cost function of reflectivity R using the input parameter values; calculating sensitivity values S for the extrema points; and obtaining an optimal value by calculating a cost function R+S.
    Type: Application
    Filed: November 21, 2003
    Publication date: May 26, 2005
    Inventors: Lav Ivanovic, Nicholas Eib, Xudong Xu
  • Publication number: 20050088640
    Abstract: The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.
    Type: Application
    Filed: April 14, 2004
    Publication date: April 28, 2005
    Inventors: Nicholas Eib, Ebo Croffie, Neal Callan
  • Publication number: 20050014075
    Abstract: A binary mask and method for improving the aerial image and mask error enhancement factor (MEEF) of binary masks. A phase edge darkening binary mask is provided which has quartz etched, preferably at a depth which corresponds to a phase shift of 180 degrees. A method of manufacturing a phase edge darkening binary mask is also provided, where the method consists of changing the phase of the layout background by etching to take advantage of the phase edge darkening as a result of light leakage through chrome.
    Type: Application
    Filed: July 18, 2003
    Publication date: January 20, 2005
    Inventors: Ebo Croffie, Kunal Taravade, Nicholas Eib
  • Patent number: 6759337
    Abstract: A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Valeriy Sukharev, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
  • Publication number: 20040128118
    Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Inventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
  • Patent number: 6413881
    Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 2, 2002
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
  • Patent number: 5897381
    Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: April 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Nicholas Eib, Jon S. Owyang
  • Patent number: 5893952
    Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: April 13, 1999
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Nicholas Eib, Jon S. Owyang
  • Patent number: 5756369
    Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: May 26, 1998
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Nicholas Eib, Jon S. Owyang
  • Patent number: 5682323
    Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. An optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: October 28, 1997
    Assignee: LSI Logic Corporation
    Inventors: Nicholas Pasch, Nicholas Eib, Jeffrey Dong