Patents by Inventor Nicholas G. Cafaro
Nicholas G. Cafaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230213932Abstract: The present specification provides systems, devices and methods for controlling an uncrewed aerial vehicle (UAV) at a public safety incident. An example method contemplates placing a UAV in a shadow mode that follows a firefighter’s movements throughout the PSI while monitoring voice activity while the UAV performs tasks such as sending images from a camera to a central server. Potential voice commands are extracted from the voice activity and associated with tasks being performed by the UAV. A machine learning dataset is built from those associations such that at future incidents the UAV can operate in a freelance mode based on detected voice commands or other contextual factors.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: Joseph C. NAMM, Nicholas G. CAFARO, Melanie A. KING, Jimmy ZONG
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Patent number: 11387859Abstract: An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal.Type: GrantFiled: June 29, 2020Date of Patent: July 12, 2022Assignee: MOTOROLA SOLUTIONS, INC.Inventors: Sumit A Talwalkar, Geetha B. Nagaraj, Nicholas G. Cafaro
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Publication number: 20210409056Abstract: An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: SUMIT A TALWALKAR, GEETHA B. NAGARAJ, NICHOLAS G. CAFARO
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Patent number: 10439850Abstract: Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.Type: GrantFiled: July 26, 2017Date of Patent: October 8, 2019Assignee: MOTOROLA SOLUTIONS, INC.Inventors: Joseph P. Heck, Christopher Calvo, Rodger W. Caruthers, Nicholas G. Cafaro, Geetha B. Nagaraj, Raul Salvi
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Publication number: 20190036747Abstract: Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Joseph P. Heck, Christopher Calvo, Rodger W. Caruthers, Nicholas G. Cafaro, Geetha B. Nagaraj, Raul Salvi
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Patent number: 9564880Abstract: Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).Type: GrantFiled: December 23, 2014Date of Patent: February 7, 2017Assignee: MOTOROLA SOLUTIONS, INC.Inventors: Robert E. Stengel, Nicholas G. Cafaro
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Publication number: 20160181980Abstract: Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: ROBERT E. STENGEL, NICHOLAS G. CAFARO
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Patent number: 8427205Abstract: A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.Type: GrantFiled: December 16, 2011Date of Patent: April 23, 2013Assignee: Motorola Solutions, Inc.Inventors: Geetha B. Nagaraj, Nicholas G. Cafaro, Robert E. Stengel, Sumit A. Talwalkar
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Patent number: 8339295Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.Type: GrantFiled: July 31, 2007Date of Patent: December 25, 2012Assignee: Motorola Solutions, Inc.Inventors: Geetha B. Nagaraj, Nicholas G. Cafaro, Ralf Hekmann, Robert E. Stengel, Scott Miller
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Patent number: 7773713Abstract: A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.Type: GrantFiled: October 19, 2006Date of Patent: August 10, 2010Assignee: Motorola, Inc.Inventors: Nicholas G. Cafaro, Robert E. Stengel
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Patent number: 7620133Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.Type: GrantFiled: November 8, 2004Date of Patent: November 17, 2009Assignee: Motorola, Inc.Inventors: Nicholas G. Cafaro, Thomas L. Gradishar, Robert E. Stengel
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Patent number: 7570096Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.Type: GrantFiled: September 26, 2007Date of Patent: August 4, 2009Assignee: Motorola, Inc.Inventors: Nicholas G. Cafaro, Thomas L. Gradishar, Robert E. Stengel
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Publication number: 20090033384Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Applicant: MOTOROLA, INC.Inventors: Geetha B. Nagaraj, Nicholas G. Cafaro, Ralf Hekmann, Robert E. Stengel, Scott Miller
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Publication number: 20080258791Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.Type: ApplicationFiled: September 26, 2007Publication date: October 23, 2008Applicant: MOTOROLA, INC.Inventors: Nicholas G. Cafaro, Thomas L. Gradishar, Robert E. Stengel
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Publication number: 20080095291Abstract: A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Inventors: Nicholas G. Cafaro, Robert E. Stengel
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Patent number: 7315215Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.Type: GrantFiled: March 8, 2006Date of Patent: January 1, 2008Assignee: Motorola,, Inc.Inventors: Nicholas G. Cafaro, Thomas L. Gradishar, Robert E. Stengel
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Patent number: 7251468Abstract: A dynamically matched mixer system (200) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator (201, 203, 205) that includes plurality of dividers (407) for providing differential local oscillator reference sources (FLO+ and FLO?) and mitigation frequency reference sources (F1 and F2) from reference oscillator (205). A mixer (209) mixes the differential local oscillator reference sources (FLO+ and FLO?) and the mitigation frequency reference sources (F1 and F2) while dynamic matching units (211, 213) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (IRF+ and IRF?) and differential baseband output signals (IBB+ and IBB?). The frequencies of the mitigation frequency reference sources (F1 and F2) are selected so as to establish a non-integer relationship to the reference oscillator (201) for mitigating the occurrence of interference with FLO+ and FLO?.Type: GrantFiled: July 14, 2004Date of Patent: July 31, 2007Assignee: Motorola, Inc.Inventors: Charles R. Ruelke, Nicholas G. Cafaro, Robert E. Stengel
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Patent number: 7031372Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.Type: GrantFiled: October 13, 2004Date of Patent: April 18, 2006Assignee: Motorola, Inc.Inventors: Andrew T. Tomerlin, Nicholas G. Cafaro, Robert E. Stengel