Abstract: An end plate for a perforating gun assembly. The end plate has a first end defining a first face, and a second end opposite the first end defining a second face. A flange resides between the first face and the second face. The end plate has a first through-opening and a second through-opening. A first bulkhead resides in the first through-opening, and is configured to closely receive a signal transmission pin. A second bulkhead resides in the second through-opening and is configured to closely receive a detonator pin. The signal transmission pin transmits detonation signals through the end plate, while the detonator pin transmits detonation signals back up the wellbore and through the end plate. The end plate may also have an opening along the second face for receiving a ground pin.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: In some embodiments, a capacitor includes a first conductive layer electrically coupled to a first terminal, a second conductive layer electrically coupled to a second terminal, a floated conductive layer disposed between the first and second conductive layers, and a plurality of non-conductive layers respectively disposed between each of the conductive layers. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a retractable ledge socket is presented. In this regard, a socket ledge is introduced to receive a processor, and to reposition to allow the processor to contact socket connections. Other embodiments are also disclosed and claimed.

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract: A planar thin film multi-layer capacitor having a high dielectric constant with a plurality of conductive through vias and a plurality of pairs of conductive through vias having a low dielectric constant and operating in a transverse electromagnetic wave mode for high frequency signals on the pairs of vias. Vias coupled to the capacitor are arranged to propagate alternate polarity. The interposer is adapted for coupling directly to a die.

Abstract: An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

Abstract: An apparatus comprises a first plurality of contacts on a first side of the apparatus adapted to interface with a corresponding plurality of contacts on an integrated circuit package. The apparatus further comprises a second plurality of contacts on a second side of the apparatus adapted to interface with a corresponding plurality of grid array leads and a plurality of capacitive storage structures coupled to the first and second plurality of contacts.

Abstract: The present disclosure describes an embodiment of an apparatus comprising a first dielectric layer having a first variation of capacitance with temperature, a second dielectric layer having a second variation of capacitance with temperature, the second variation of capacitance with temperature being different than the first variation of capacitance with temperature, and a conductive layer sandwiched between the first and second dielectric layers. Also described is an embodiment of a process comprising forming a first dielectric layer comprising a dielectric having a first composition, stacking a conductive layer on the first dielectric layer, and stacking a second dielectric layer on the conductive layer, the second dielectric layer having a second composition different than the first composition. Other embodiments are also described and claimed.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: A planar thin film multi-layer capacitor having a high dielectric constant with a plurality of conductive through vias and a plurality of pairs of conductive through vias having a low dielectric constant and operating in a transverse electromagnetic wave mode for high frequency signals on the pairs of vias. Vias coupled to the capacitor are arranged to propagate alternate polarity. The interposer is adapted for coupling directly to a die.