Patents by Inventor Nicholas J. Chiolino

Nicholas J. Chiolino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiwire plate-enclosed ball-isolated single-substrate silicon-carbide-die package
    Patent number: 11723154
    Abstract: A silicon carbide die package with multiple wire access points utilizing top and bottom enclosure plate clamps housing a silicon carbide die on a printed wiring board with wire contact pads, and a set of set screws providing downward pressure from the top enclosure plate inside the center of a cylindrical isolation housing to an isolation ball positioned above a clamp discs to clamp a wire end between the clamp disc and the wire contact pad.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 8, 2023
    Inventors: Nicholas J. Chiolino, A. Matthew Francis, Matthew W. Barlow, Jacob Kupernik
  • Direct application additive manufacturing for conductive wafer interconnect
    Patent number: 11217659
    Abstract: An improved silicon carbide wafer using direct application conductive ink interconnects positioned on printing connection pads. The conductive ink interconnected can be routed to form a custom length resistive trace for a device after fabrication and measurement of the device.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 4, 2022
    Inventors: Matthew W. Barlow, Nicholas J. Chiolino, Anthony M. Francis, James A. Holmes
  • RADIATION-HARDENED D FLIP-FLOP CIRCUIT
    Publication number: 20210257999
    Abstract: A flip-flop and latch circuit is disclosed. The circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: Bin Li, David Bostedo, Landon J. Caley, Nicholas J. Chiolino, Patrick Fleming, David D. Moser
  • Radiation-hardened D flip-flop circuit
    Patent number: 10998890
    Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 4, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Bin Li, David Bostedo, Landon J. Caley, Nicholas J. Chiolino, Patrick Fleming, David D. Moser
  • RADIATION-HARDENED D FLIP-FLOP CIRCUIT
    Publication number: 20190363699
    Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.
    Type: Application
    Filed: December 29, 2017
    Publication date: November 28, 2019
    Inventors: Bin Li, David Bostedo, Landon J. Caley, Nicholas J. Chiolino, Patrick Fleming, David D. Moser