Abstract: An image display system with one or more client computers in selective communication with a visual server having image processing capabilities. The client computer generates image modifying data corresponding to a generated image, and transmits the data to the visual server. The visual server receives the image-modifying data, generates a modified image based upon the image-modifying data, and transmits the modified image as compressed data to the client. The client decompresses the modified image data and displays the modified image. In the system, the visual server and client can provide a sequential display of modified frames on client to support animation with complex 3-dimensional graphics.

Abstract: A system and methods for a novel user interface of a touch sensitive screen for pocket device. The user interface contains display items and action tabs. Display items are configured to be draggable if being dragged at substantially horizontal direction; display items are configured to be scrollable if being dragged at substantially vertical direction. Dragging and releasing a draggable item to an action tab causes a specified action or a sequence of actions being applied to the item.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A graphics accelerator with a byte-tiled memory architecture, and a high-speed image download path which provides higher bandwidth than the message-passing pipeline.

Abstract: A virtual memory page table wherein each entry specifies the size of an optional larger block of pages which is optionally associated with any particular page. This achieves a backward-compatible way to achieve variable page size with minimal added overhead.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A buffer and table structure for reordering out-of-order evictions from a write-combine buffer. In a preferred embodiment, a first-in first-out (FIFO) buffer is used.

Abstract: A graphics rendering system and method utilizing a unified memory space for a depth-buffer and the back framebuffer. To provide very high resolution with a limited memory, each primitive is rendered once to provide depth values, to determine which pixels of each primitive are displayed, and a second time to store the color values of pixels which are to be displayed. A flag bit is used to ensure that depth data and color data, which coexist in a common memory space, cannot be confused or interchanged.

Abstract: A system and method for computer graphics generation which uses a local library of graphics textures. When an application, run either locally or over a communications system, requires texture-mapped graphics, texture data is retrieved from the local library instead of transmitted to the system.

Abstract: A system and method for improving the efficiency of DMA transfers. In particular, a “continue” command is provided for DMA block transfers. In practice, this command allows the system to begin a DMA transfer before the entire size of the transfer block is known and to continue the transfer, avoiding an additional setup time, by simply instructing the DMAC to continue sending data in the same manner. Transfer continuation is accomplished by resetting the DMA transfer count register to a new value without ever stopping the transfer. Each time the transfer count runs down, the system resets it to a higher value and continues the transfer rather than initializing a second transfer.

Abstract: A rendering processor with texture processing capability, in which textures are retrieved from local storage as n.times.n patches. By retrieving a multi-pixel patch on each memory read, the frequency of memory accesses and page breaks in particular are reduced, resulting in a lower memory access time overhead.

Abstract: A system and method for performing 3D graphics copying operations in such a manner as to produce both a smooth image and smooth edges. The alpha value of each pixel is used to mark the pixels which are and are not part of the image to be copied, and removes unwanted pixels from bilinear filtering operations. After filtering, the resultant alpha values along the edges of the object are used to eliminate unwanted pixels, and to blend the object into the background of the image, which reduces or eliminates the "blocky" edges.