Abstract: An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

Abstract: A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the specific search key is made at the network packet search engine. A determination is made at the network packet search engine regarding whether the longest prefix match comprises an overall longest prefix match among the cascaded network packet search engines such that any of the cascaded network packet search engines may comprise the overall longest matching prefix independently of position relative to the other cascaded network packet search engines.

Abstract: An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

Abstract: There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.

Abstract: A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the specific search key is made at the network packet search engine. A determination is made at the network packet search engine regarding whether the longest prefix match comprises an overall longest prefix match among the cascaded network packet search engines such that any of the cascaded network packet search engines may comprise the overall longest matching prefix independently of position relative to the other cascaded network packet search engines.

Abstract: A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.

Abstract: A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.

Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: There is disclosed a cache memory for use in a data processor. The cache memory comprises a first static random access memory (SRAM) that receives up to N incoming bytes of data on an input bus and that stores the up to N incoming bytes of data in an N-byte addressable location. M incoming bytes of data may be written in each of the N-byte addressable locations during a write operation (where M may be less than N) and the M written bytes of data and N−M unwritten bytes of data are output from each N-byte addressable location on an output bus of the first SRAM during each write operation. The cache memory also comprises a parity generator coupled to the first SRAM that receives the M written bytes of data and the N−M unwritten bytes of data and generates at least one write parity bit associated with the M written bytes of data and the N−M unwritten bytes of data.

Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: In a computer system, a processing unit generates a read request and sends it to a cache. If data for the read request is not in the cache, the cache forwards the request to a bus interface unit. If the forwarded request does not fall within the address range of any bus read transaction stored in the bus interface unit, the bus interface unit stores a new bus read transaction corresponding to the forwarded request and sends an identifier for the new transaction to the processing unit. In one preferred embodiment, if the forwarded request falls within the address range of one of the bus read transactions stored in the bus interface unit, the bus interface unit discards the forwarded request and sends an identifier for the one transaction to the processing unit. Additionally, a method of processing read requests is provided. A read request is stored in a buffer and sent to a cache.

Abstract: A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal.

Abstract: A bus interface unit includes multiple pointer queues coupled to a random-access transaction buffer. The transaction buffer stores address and data information for each requested bus transaction, and the pointer queues store pointers to the transaction information stored in the transaction buffer. The bus interface unit uses the pointers to order the transactions stored in the random-access transaction buffer. In one preferred embodiment, one pointer queue is used to store pointers for order dependent transactions, and another pointer queue is used to store pointers for non-order dependent transactions. In some embodiments, when an issued transaction is deferred by its target, the deferred transaction's information is maintained in the transaction buffer. Additionally, a method is provided for storing address, data, and ordering information for requested bus transactions. The address and data information for requested transactions is stored as entries in a random-access buffer.

Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue.

Abstract: A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus.

Abstract: An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Abstract: A computer system includes a central processing unit (CPU), system read-only memory (ROM), a random access memory (RAM) and a system controller. The system ROM includes a reset vector. A portion of the RAM is used to shadow the system ROM. The system controller is connected between the CPU, the system ROM and the RAM. The system memory includes an internal memory for storing first data. The system memory also includes logic which, in response to receiving an access to a reset vector stored in the system ROM, returns the first data stored in the internal memory.

Abstract: A method for preventing deadlocks is used in a computing system in which a host bus is connected to a first input/output bus through a first bridge and the first input/output bus is connected to a second input bus through a second bridge. When transferring data from a first input/output device on the second input/output bus to a memory on the host bus, the first input/output device requests mastership of the second input/output bus. Before granting mastership to the first input/output device, the second bridge instructs the first bridge to flush and disable write buffers within the first bridge. After the write buffers have been flushed, the first input/output device is granted mastership of the second input/output bus. The second bridge requests mastership of the first input/output bus by asserting a request signal on a request line. The first bridge then obtains mastership of the host bus in order to allow the transfer of the data from the first input/output device to the memory.

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit.

Abstract: A dynamic arbitration system for controlling the data transfer between primary and secondary buses in a personal computer has master and target components on both buses. Primary and secondary bus arbiters are included in a bridge circuit, and initially operate independently of one another in a concurrent arbitration mode of operation. This avoids primary bus interruption for secondary-to-secondary transfers and optimizes the primary bus bandwidth. Whenever a secondary-to-primary bus data transfer cycle is detected, the bridge circuit switches the primary and secondary bus arbiters to an interlocked mode of operation. The interlocked arbitration mode of operation is maintained until the next secondary-to-secondary cycle is detected; whereupon the bridge circuit causes the primary and secondary bus arbiters to be switched back to the concurrent arbitration mode of operation.