Abstract: A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error.

Abstract: A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

Abstract: A computer-based method and program for improving a design of a circuit through analysis of a computer stored model of the circuit. Individual synchronization points are identified in the circuit at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at the synchronization point. The timing of the circuit is verified based on the individual synchronization points.

Abstract: In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.