Patents by Inventor Nicholas Neal
Nicholas Neal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11998758Abstract: Methods and related devices for impinging light on tissue, for example within a body of a patient, to induce various biological effects are disclosed. Biological effects may include at least one of inactivating and/or inhibiting growth of one or more pathogens, upregulating a local immune response, stimulating enzymatic generation of nitric oxide to increase endogenous stores of nitric oxide, releasing nitric oxide from endogenous stores of nitric oxide, and inducing an anti-inflammatory effect. Wavelengths of light are selected based on intended biological effects for one or more of targeted tissue types and targeted pathogens. Light treatments may provide multiple pathogenic biological effects, either with light of a single wavelength or with light having multiple wavelengths. Devices and methods for light treatments are disclosed that provide light doses for inducing biological effects on various targeted pathogens and targeted tissues with increased efficacy and reduced cytotoxicity.Type: GrantFiled: January 13, 2021Date of Patent: June 4, 2024Assignee: KNOW Bio, LLCInventors: Nathan Stasko, David T. Emerson, Adam Cockrell, F. Neal Hunter, Michael John Bergmann, Rebecca McDonald, Nicholas William Medendorp, Jr., Gerald H. Negley, Katelyn P. Reighard
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Publication number: 20240136326Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
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Patent number: 11942393Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.Type: GrantFiled: February 4, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Mitul Modi, Nicholas Neal
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Patent number: 11901262Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.Type: GrantFiled: January 24, 2019Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Nicholas Neal, Zhimin Wan, Shankar Devasenathipathy, Je-Young Chang
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Patent number: 11901333Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: GrantFiled: October 8, 2019Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Ram S. Viswanath, Nicholas Neal, Mitul Modi
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Patent number: 11854935Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: GrantFiled: February 19, 2020Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
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Patent number: 11832419Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: GrantFiled: December 20, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
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Patent number: 11804418Abstract: A heat exchange module, comprising an array of microchannels, where the array of microchannels extends in a first direction, and are separated from one another by a first sidewall. The array of microchannels is over a cold plate. A first array of fluid distribution channels is stacked over the array of microchannels and extend in a second direction that is substantially orthogonal to the first direction. The first array of fluid distribution channels extends from the first manifold and terminate between a first manifold and a second manifold. A second array of fluid distribution channels is stacked over the array of microchannels. The first array of fluid distribution channels and the second array of the fluid distribution channels are fluidically coupled to the microchannel array. A wall extends into the microchannel array below a second sidewall separating ones of the first array and ones of the second array of fluid distribution channels.Type: GrantFiled: January 11, 2019Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Je-Young Chang, Jae Kim, Ravindranath Mahajan
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Publication number: 20230343723Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
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Patent number: 11776864Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.Type: GrantFiled: July 15, 2019Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Edvin Cetegen, Nicholas Neal, Sergio Chan Arguedas
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Publication number: 20230238355Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
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Patent number: 11640929Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.Type: GrantFiled: December 20, 2018Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Divya Mani, Nicholas Haehn
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Publication number: 20230128903Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
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Patent number: 11594463Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.Type: GrantFiled: October 11, 2018Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas Haehn
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Patent number: 11587843Abstract: Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.Type: GrantFiled: December 13, 2018Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Prasad Ramanathan, Nicholas Neal, Chandra Mohan Jha
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Publication number: 20210257277Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
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Publication number: 20210249330Abstract: Embodiments herein relate to systems, techniques, and/or processes directed to a composite thermal matrix structure to provide thermal conductivity within a package. The composite thermal matrix may include a first material that is substantially solid and a second material that is liquid and absorbed into the first material. A package may include the composite thermal matrix within an integrated heat sink coupled with a printed circuit board and encapsulating one or more die where the thermal matrix structure is in a state of compressive stress within the heat sink. The thermal matrix structure may expand and contract as the heat sink warps during thermal cycling to maintain constant thermal conductivity with low stress on the package.Type: ApplicationFiled: February 6, 2020Publication date: August 12, 2021Inventors: Nicholas S. Haehn, Nicholas Neal
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Publication number: 20210242107Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Mitul MODI, Nicholas NEAL
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Publication number: 20210195798Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Nicholas NEAL, Nicholas S. HAEHN, Je-Young CHANG, Kyle ARRINGTON, Aaron MCCANN, Edvin CETEGEN, Ravindranath V. MAHAJAN, Robert L. SANKMAN, Ken P. HACKENBERG, Sergio A. CHAN ARGUEDAS
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Publication number: 20210104490Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: October 8, 2019Publication date: April 8, 2021Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI