Abstract: Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit.

Abstract: Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.

Abstract: Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit.

Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.

Abstract: Method and apparatus for data storage. In some embodiments, a solid-state memory includes an array of non-volatile memory cells arranged into erasable blocks. A register stores a multi-bit sequence value. A controller randomizes input data to be written to a selected erasable block by combining the input data with the multi-bit sequence value shifted by a number of bit locations responsive to an accumulated access count for the selected erasable block.

Abstract: Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit.

Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.

Abstract: Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.

Abstract: Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit.

Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.

Abstract: Method and apparatus for data storage. In some embodiments, a solid-state memory includes an array of non-volatile memory cells arranged into erasable blocks. A register stores a multi-bit sequence value. A controller randomizes input data to be written to a selected erasable block by combining the input data with the multi-bit sequence value shifted by a number of bit locations responsive to an accumulated access count for the selected erasable block.

Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.

Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.