Patents by Inventor Nicholas P. Malaya

Nicholas P. Malaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220414456
    Abstract: The described embodiments include an electronic device having a processor. The processor performs operations for handling watermarks in files. As part of the operations, the processor processes a portion of a file in a classification neural network to determine whether a watermark is present in the portion of the file. Based on a result of the processing, the processor performs an update associated with the watermark in the portion of the file. The processor then provides the updated portion of the file.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Nicholas P. Malaya, William W. Freitag, JR.
  • Patent number: 11481637
    Abstract: An electronic device that includes a controller functional block and a computational functional block having one or more computational elements performs operations associated with a training operation for a generative adversarial network, the generative adversarial network including a generative network and a discriminative network. The controller functional block determines one or more characteristics of the generative adversarial network. Based on the one or more characteristics, the controller functional block configures the one or more computational elements to perform processing operations for each of the generative network and the discriminative network during the training operation for the generative adversarial network.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 25, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicholas P. Malaya
  • Patent number: 11216250
    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: January 4, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nicholas P. Malaya, Elliot H. Mednick
  • Patent number: 10936697
    Abstract: A method includes storing a first portion of a sparse triangular matrix in a local memory and launching a kernel for executing a set of workgroups. The first portion includes a plurality of row blocks, and each workgroup in the set of workgroups is associated with one of the plurality of row blocks. The method also includes, for each workgroup in the set of workgroups, solving the row block. The row block is solved by, for each row segment of a first subset of row segments in the row block, calculating a partial sum for the row segment based on one or more matrix elements in the row segment, and writing the partial sum to a remote memory of a first remote processing unit prior to terminating the kernel.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 2, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khaled Hamidouche, Michael W. LeBeane, Nicholas P. Malaya, Joseph L. Greathouse
  • Publication number: 20200034405
    Abstract: A method includes storing a first portion of a sparse triangular matrix in a local memory and launching a kernel for executing a set of workgroups. The first portion includes a plurality of row blocks, and each workgroup in the set of workgroups is associated with one of the plurality of row blocks. The method also includes, for each workgroup in the set of workgroups, solving the row block. The row block is solved by, for each row segment of a first subset of row segments in the row block, calculating a partial sum for the row segment based on one or more matrix elements in the row segment, and writing the partial sum to a remote memory of a first remote processing unit prior to terminating the kernel.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Inventors: Khaled Hamidouche, Michael W. LeBeane, Nicholas P. Malaya, Joseph L. Greathouse
  • Publication number: 20190385064
    Abstract: An electronic device that includes a controller functional block and a computational functional block having one or more computational elements performs operations associated with a training operation for a generative adversarial network, the generative adversarial network including a generative network and a discriminative network. The controller functional block determines one or more characteristics of the generative adversarial network. Based on the one or more characteristics, the controller functional block configures the one or more computational elements to perform processing operations for each of the generative network and the discriminative network during the training operation for the generative adversarial network.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Inventor: Nicholas P. Malaya
  • Publication number: 20190171420
    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 6, 2019
    Inventors: Nicholas P. Malaya, Elliot H. Mednick