Abstract: An image sensor may include a pixel array and associated readout paths calibration circuitry. The image sensor may include first column readout circuits formed along a first edge of the pixel array and second column readout circuits formed along a second opposing edge of the pixel array. The readout paths calibration circuitry may include one or more first calibration readout circuits located by the first edge of the array, one or more second calibration readout circuits located by the second edge of the array, and an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits and the one or more second calibration readout circuits. The one or more second calibration readout circuits and the second column readout circuits can receive a reference voltage that is dynamically adjusted based on the error signal.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may include an image sensor pixel array. The image sensor pixel array may include active image sensor pixels that generate image data based on incident light and reference pixels that are optically black for generating reference data for noise compensation. Sets of reference pixels in the same row may be coupled to respective shared readout paths in a source follower binning configuration. The shared readout path may be could to downstream readout circuits. The use of shared readout paths for the reference pixels can reduce the number of reference pixel readout paths. If desired, pixel circuitry may be implemented on a first die, while readout circuitry and at least a portion of the reference pixel readout paths may be implemented on a second die mounted to the first die.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: An image sensor may be implemented by mounting a first die to a second die. The first die may include an image sensor pixel array having active pixels and non-active pixels, while the second die may include pixel control and readout circuitry that are coupled to the image sensor pixel array via inter-die connections. The image sensor pixel array may have pixel columns in excess of corresponding column readout paths in the pixel readout circuitry and/or pixel rows in excess of corresponding sets of row control paths in the pixel control circuitry. A select set of inter-die connections may be implemented to provide connections between a desired set of pixel columns and the limited number of column readout paths and to provide connections between a desired set of pixel rows and the limited number of sets of row control paths.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.

Abstract: An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

Abstract: An image sensor may include a pixel array having pixels arranged in rows and columns, column readout circuitry, and control circuitry. Column readout circuitry may include corresponding readout circuits each coupled to a corresponding column path for a respective column of pixels. The readout circuits may each include signal processing circuits such as correlated double sampling circuitry and analog-to-digital converter circuitry. To reduce peak-to-average power ratio, during the signal processing operations for each pixel row, the control circuitry may control the signal processing circuits to perform time-domain multiplexing across the pixel columns to activate the signal processing circuits at varied times within the row time. If desired, the pattern of time-domain multiplexing may be varied across the signal processing operations for different pixel rows and/or for different image frames.

Abstract: An imaging device may have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The rows of pixels may receive drive signals from row driver circuitry, and the drive signals may be sent from timing circuitry based on the locations of rows within the array. In particular, rows closer to the readout circuitry may require less settling time and therefore be driven faster than the rows further from the readout circuitry. All of the rows may be driven in a single direction, or the array of pixels may have a cut, in which case rows above the cut may be driven up and rows below the cut may be driven down. A frame buffer may be used to store the signals generated by the rows of pixels and may account for the asynchronous read out of image data.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may include a pixel array having pixels arranged in rows and columns, column readout circuitry, and control circuitry. Column readout circuitry may include corresponding readout circuits each coupled to a corresponding column path for a respective column of pixels. The readout circuits may each include signal processing circuits such as correlated double sampling circuitry and analog-to-digital converter circuitry. To reduce peak-to-average power ratio, during the signal processing operations for each pixel row, the control circuitry may control the signal processing circuits to perform time-domain multiplexing across the pixel columns to activate the signal processing circuits at varied times within the row time. If desired, the pattern of time-domain multiplexing may be varied across the signal processing operations for different pixel rows and/or for different image frames.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: An image sensor may include a pixel array coupled to column readout circuitry. The pixel array may be split into multiple sub-arrays. Readout circuitry may be shared between multiple columns in each sub-array or in the pixel array. The readout circuitry may be coupled to at least first and second pixels in first and second different columns. The readout circuitry may include amplifier circuitry that receives signals from both the first and second pixels. Two input capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. Two feedback capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. The readout circuitry may be configured to perform a shared reset level readout operation for the first and second pixels and to perform separate correlated double sampling readout operations for the first and second pixels.

Abstract: An imaging device may have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The rows of pixels may receive drive signals from row driver circuitry, and the drive signals may be sent from timing circuitry based on the locations of rows within the array. In particular, rows closer to the readout circuitry may require less settling time and therefore be driven faster than the rows further from the readout circuitry. All of the rows may be driven in a single direction, or the array of pixels may have a cut, in which case rows above the cut may be driven up and rows below the cut may be driven down. A frame buffer may be used to store the signals generated by the rows of pixels and may account for the asynchronous read out of image data.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.