Abstract: A method of integrating repeaters into an integrated circuit design model includes specifying a geometry of a plurality of separate cell blocks. These cell blocks are locations on a chip die supporting appropriate functional capabilities, such as arithmetic and logic functions, decoders, input/output, etc. A list identifying top level nets connecting the cell blocks is then generated and locations along these top level nets exceeding a maximum signal transmission criteria (e.g., RC interconnect constraints) are identified. Repeater constraint regions are defined apart from the cell blocks and include one or more of the locations identified. A list is then generated of top level nets to be repeated at respective repeater constraint regions. An HDL representation is generated of repeater blocks for placement within each of the repeater constraint regions. Wiring directives may then be automatically generated connecting the HDL representation of repeater blocks into the integrated circuit design model.

Abstract: Connection lines are routed within an integrated circuit. A first set of the connection lines are pre-routed. The first set of connection lines carry signals which have a higher likelihood of being influenced by crosstalk. The first set of connection lines are routed to tracks where minimal capacitive coupling will result. For example, this may be in a track immediately adjacent to a power line or a ground line. Alternatively, or in addition, this may be in a track between two empty tracks. After the first set of connection lines have been routed, a second set of connection lines are routed. The second set of connection lines carry signals which have a lower likelihood of being influenced by crosstalk. The second connection lines are routed to tracks which are not utilized by the first set of connection lines.

Abstract: Signals are routed within a routing channel between a first logic block and a second logic block. A power signal within a power conductor is routed as part of a bottom layer of the routing channel. The bottom layer is located above a substrate for the integrated circuit. A ground signal is also routed within a ground conductor as part of the bottom layer of the routing channel. Data lines are routed in a top layer of the routing channel. The data lines carry data signals within the routing channel. Connection lines are routed within a middle layer of the routing channel. The middle layer is between the bottom layer of the routing channel and the top layer of the routing channel. The connecting lines connect a subset of the data lines in the top layer, the ground conductor in the bottom layer and the power conductor in the bottom layer to the first logic block and to the second logic block.