Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

Abstract: A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal.

Abstract: A long term response enhancement for a digital phase-locked loop is implemented to provide a relatively minor change in the phase of the output signal over a relatively long period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur between successive input signals, producing an output signal when the two numbers agree.

Abstract: A data mover for moving blocks of data stored in a first location of the working store of a data processing system to a second location in the working store. The data mover is provided with the necessary registers, switches, counters and control circuits to issue read and write commands to the working store, to receive and store in registers data read out of the working store as the result of its having issued a read command, and to write data read out of working store and stored in its registers in response to a read command issued by the data mover into another location in the working store. These steps are repeated until a block, measured in thousands, of data words has been moved from the first to the second location. The address preparation circuits of the high speed multiplexer of the data processing system through which the data mover communicates with the working store of the system is used to provide a substitute memory command for one of the two types of memory commands issued by the data mover.

Abstract: This relates to a digital data recovery system for decoding group coded data bits stored on magnetic tape whereon a "1" is represented by a flux reversal and an "0" is represented by the absence of a flux reversal with no more than two successive zeros throughout the data record. Input logic detects transitions of input data and forwards this information to an envelope detector which determines if subsequent transitions represent valid data. The presence of valid data enables a data rate detector which determines the average data rate. An output sequencer determines when a decoded output data bit should be generated and its proper polarity.