Abstract: In order to ensure continued charging of electric vehicles when a charging station is not currently received an input power from an external power source, the systems and methods disclosed herein provide for operation of the charging station in a resilient operating mode in which an operating current is derived from a charge previously stored in a battery of the charging station. The operating current is produced by a resilient power subsystem within the charging station using the stored charge and is provided by the resilient power subsystem to one or more system components within the charging station in order to enable continued operation of the charging station, including enabling continuing vehicle charging during a time interval in which the charging station is not receiving input power from an external power source.

Abstract: In order to ensure reliable power for charging electric vehicles is available at each charging station at a charging site having multiple charging stations, the systems and methods disclosed herein provide for charge transfers between batteries of such charging stations. A plurality of charging stations at a charging site are connected via a direct current (DC) bus in order to transfer energy between the charging stations, such as to balance the energy stored at the respective batteries of the charging stations. Each charging station includes a system controller controlling operation of the charging station and a DC bus connection to provide DC current from the battery to the DC bus and to provide DC current from the DC bus to the battery, as controlled by the system controller. A centralized management system may also communicate with and control aspects of operation of the respective system controllers of the charging stations.

Abstract: In order to ensure reliable power for charging electric vehicles is available at each charging station at a charging site having multiple charging stations, the systems and methods disclosed herein provide for charge transfers between batteries of such charging stations. A plurality of charging stations at a charging site are connected via local alternating current (AC) circuit in order to transfer energy between the charging stations, such as to balance the energy stored at the respective batteries of the charging stations. Each charging station includes a system controller controlling operation of the charging station and a bidirectional inverter to convert AC input power from a power grid or the local AC circuit to direct current (DC) power for storage in a battery of the charging station and to convert DC power from the battery to AC output power to the local AC circuit, as controlled by the system controller.

Abstract: A vehicle charging apparatus is described herein, which may include a battery pack comprising a plurality of individual batteries, a power input port receiving electrical power at a first wattage, an AC-to-DC conversion circuit configured to provide DC power to charge groups of batteries in the plurality of individual batteries, a power conversion circuit configured to condition a DC output of at least one group of batteries to provide a charging current output to a vehicle via a coupling, and a processing circuit configured to control the power conversion circuit to provide the charging current at a second wattage greater than the first wattage. The first wattage may be actively or inherently limited to a level less than the second wattage in order to provide fast DC charging with a limited power input.

Abstract: Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

Abstract: One example discloses a power management device, including: a first port configured to be coupled to a first power source; a second port configured to be coupled to a second power source; a switched capacitor converter; and an inductor coupled in parallel with a switch; wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch; and wherein another end of the inductor coupled in parallel with the switch, is coupled between the switched capacitor converter and the second port.

Abstract: One example discloses a power management device, including: a first port configured to be coupled to a first power source; a second port configured to be coupled to a second power source; a switched capacitor converter; and an inductor coupled in parallel with a switch; wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch; and wherein another end of the inductor coupled in parallel with the switch, is coupled between the switched capacitor converter and the second port.

Abstract: This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Abstract: In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract: In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract: In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.

Abstract: This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.

Abstract: In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.

Abstract: In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.

Abstract: Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

Abstract: In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.