Abstract: A system for authorizing respective initiation of a plurality of remote services by or for mobile device users. The system comprises a processor, and storage devices, at an authorization service (AS). A storage device stores public key portions of authentication tokens for mobile device users and remote service identifiers. Stored program code executable by the AS processor receives only public key portions of authentication tokens created on mobile devices. For actions to initiate a remote service, the program code is for receiving a remote service identifier and challenge information from a remote service server, transmitting at least a portion of the challenge information to a user's mobile device, receiving messages from the user's mobile device, validating at least one of the received messages using the stored public key portion of the authentication token for the user, and if validated, initiating the remote service.

Abstract: A system for authorizing respective initiation of a plurality of remote services by or for mobile device users. The system comprises a processor, and storage devices, at an authorization service (AS). A storage device stores public key portions of authentication tokens for mobile device users and remote service identifiers. Stored program code executable by the AS processor receives only public key portions of authentication tokens created on mobile devices. For actions to initiate a remote service, the program code is for receiving a remote service identifier and challenge information from a remote service server, transmitting at least a portion of the challenge information to a user's mobile device, receiving messages from the user's mobile device, validating at least one of the received messages using the stored public key portion of the authentication token for the user, and if validated, initiating the remote service.

Abstract: A system and method optimizing data throughput to a processor from a storage device having sequential data access capabilities where the processor enables its data cache for memory operations involving the storage device. The system includes a processor coupled to the data storage device, e.g., a NAND flash memory. The processor establishes an address window used as a cache (CW) for reading data from the flash memory and also establishes a non-cacheable address window (NCW) for commands, address delivery and writes to the flash memory. The CW is sized to be larger than the processor data cache to ensure that reads from the flash memory always encounter a cache-miss so that read data is obtained directly from the flash memory. By reading through the CW from the flash memory, the processor takes advantage of bursting, pipelining and data prefetch efficiencies which significantly increase data throughput.