Abstract: Transformerless ethernet controller. A method for isolating an ethernet controller, having a transceiver associated therewith, from a twisted wire transmission line is provided. The power supply of the transceiver is DC isolated from system power supply. The data side of the ethernet controller is DC isolated from the transceiver for both transmit and receive data. The transceiver is directly connected to the transmission line with no DC isolation.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Abstract: Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.

Abstract: Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.

Abstract: A pad calibration circuit with on-chip resistor. An integrated circuit with an impedance terminated output terminal is disclosed. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between the source and the output terminal to define the input impedance of the output terminal.

Abstract: Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.

Abstract: Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.

Abstract: A pad calibration circuit with on-chip resistor. An integrated circuit with an impedance terminated output terminal is disclosed. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between the source and the output terminal to define the input impedance of the output terminal.

Abstract: A PSD template for an HDSL2 transmission system includes three regions, a full-duplex region for both upstream and downstream transmission, and two half-duplex regions, a first duplex region for containing substantially upstream power and a half-duplex region for containing substantially downstream power.

Abstract: An oversampling converter for converting an analog input signal to a high resolution digital equivalent is provided. The oversampling converter uses sigma delta modulation utilizing single integration. A plurality of quantization circuits provide a plurality of output signals, each output signal containing data information and an error component. Each quantization circuit performs an integration of a difference of an input signal and a feedback signal before quantizing the integrated signal as one of the output signals. A filter, such as a decimation filter, is coupled to the converter for receiving the multiple outputs of the converter and providing a filtered converted digital output signal.