Abstract: An embodiment of the invention is directed at a method of processing multiple delayed write transactions, such as PCI transactions, by a bridge. The method involves receiving a number of requests for delayed write transactions on an initiating side of the bridge, and storing received transaction information for each of the requests in a separate one of a number of storage elements. An element containing newly received transaction information is marked valid if no received transaction information in other elements matches the newly received transaction information. Then, a delayed write transaction corresponding to the valid element is mastered on a target side of the bridge. If the corresponding delayed write transaction is completed on the target side, then the valid element is marked as complete. Thereafter, a new request received on the initiating side is signaled a successful termination if received transaction information for the new request matches that stored in the valid and complete element.

Abstract: Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.

Abstract: A method of handling read transactions to improve latency and promote streaming across a bridge. When an initiator returns to retrieve the read data associated with a previously enqueued transaction, the bridge will insert one or more wait states if the enqueued transaction is being mastered and no data has been received in a buffer of the bridge from the target, or if some but not a sufficient amount of data has been received from the target. The bridge continues to hold the initiator until the buffer contains sufficient read data whereupon the bridge will deliver the read data from the buffer to the initiator.

Abstract: An embodiment of the invention is a bridge having a transaction queue for storing transaction information for each of a number of enqueued posted write transactions, a data queue for simultaneously storing transaction data for each of the enqueued transactions, the transaction data having been received through slave logic of the bridge to be delivered through master logic of the bridge, and a controller for managing the transaction and data queues in response to the transaction information, the bridge being further configured to dynamically allow the transaction data for a single enqueued transaction to occupy the maximum available space in the data queue.

Abstract: A transmit circuit operable to synchronize a data transmission is disclosed. The transmit circuit comprises a first circuit configured to transmit a plurality of data segments. The transmit circuit further comprises a second circuit coupled to the first circuit. The second circuit is configured to generate a strobe signal indicating the transmission of a first data segment of the plurality of data segments. The transmit circuit also comprises a third circuit coupled to the second circuit. The third component is configured to receive an acknowledge signal. Based on a logic transition of the acknowledge signal, the third circuit determines the transmission of a second data segment of the plurality of data segments.

Abstract: A method and apparatus are provided for testing memory locations of embedded memories or on-board caches of a micro-controller, a micro-processor or a CPU-based integrated circuit through use of a test access port (TAP) such as the IEEE TAP described in "IEEE Standard Test Access Port and Boundary-Scan Architecture" (IEEE Std. 1149.1-1990). The TAP is utilized to serially shift address, data and command information provided by an external host into respective fields of a memory access register (MEMACC) located within a memory interface unit (MIU) of the CPU-based IC. Responsive to the command information, the TAP requests access to the IC's memory bus via the MIU. Next, the address, data and command information for accessing the embedded memory are serially shifted into the MEMACC.

Abstract: The present invention provides a method and apparatus for enabling asynchronous, bi-directional communication between the CPU of a CPU-based integrated circuit and an external system having digital logic for effecting transitions between operating modes of the integrated circuit. The apparatus is utilized to inform the CPU of an interrupt request transmitted from the external system and to subsequently inform the external system of an interrupt acknowledgment transmitted from the CPU. This is accomplished by providing the CPU with a first associated register and the external system with a second associated register in addition to selector means coupled in parallel to the first register and the second register. The selector means has as a first input a first value forming an interrupt request stored in the first register and as a second input a second value forming an interrupt acknowledgment stored in the second register.