Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically coupled to a buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

Abstract: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

Abstract: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

Abstract: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

Abstract: A method and apparatus that tests and observes how an embedded DRAM is being accessed by a logic circuit controlling the DRAM is provided. The test and observe method and apparatus pipes the outputs of the logic, which is used as inputs to the embedded DRAM, to an observation device. The outputs of the logic device are then observed at the observation device to determine how the DRAM is being accessed. In addition, information concerning what data is being trapped and when may be output to the observation device to determine setup and hold times for the DRAM.

Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.