Patents by Inventor Nicol Hofmann
Nicol Hofmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11861325Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.Type: GrantFiled: September 21, 2021Date of Patent: January 2, 2024Assignee: International Business Machines CorporationInventors: Nicol Hofmann, Michael Klein, Petra Leber, Kerstin Claudia Schelm
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Publication number: 20230129750Abstract: A processor is used for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit, with three input floating-point operands A, B, C, wherein at least one of the operands A, B, C is substituted by at least one value of a predefined operand value set.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Inventors: Razvan Peter Figuli, Cedric Lichtenau, Tina Babinsky, Nicol Hofmann, Burkhard Steinmacher-Burow
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Patent number: 11269651Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.Type: GrantFiled: September 10, 2019Date of Patent: March 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Klein, Nicol Hofmann, Cedric Lichtenau, Osher Yifrach
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Publication number: 20220004361Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Inventors: Nicol HOFMANN, Michael KLEIN, Petra LEBER, Kerstin Claudia SCHELM
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Patent number: 11210064Abstract: A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.Type: GrantFiled: July 30, 2019Date of Patent: December 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefan Payer, Silvia Melitta Mueller, Nicol Hofmann, Razvan Peter Figuli
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Patent number: 11188299Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.Type: GrantFiled: July 31, 2019Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicol Hofmann, Michael Klein, Petra Leber, Kerstin Claudia Schelm
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Patent number: 11175890Abstract: Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.Type: GrantFiled: April 30, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerstin Claudia Schelm, Petra Leber, Nicol Hofmann, Michael Klein
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Patent number: 11159183Abstract: A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.Type: GrantFiled: June 26, 2019Date of Patent: October 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicol Hofmann, Michael Klein, Kerstin Claudia Schelm, Razvan Peter Figuli
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Publication number: 20210073000Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.Type: ApplicationFiled: September 10, 2019Publication date: March 11, 2021Inventors: MICHAEL KLEIN, NICOL HOFMANN, CEDRIC LICHTENAU, OSHER YIFRACH
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Publication number: 20210048982Abstract: A method includes masking a first fraction to generate a masked first fraction according to a comparison of a first exponent associated with the first fraction and a second exponent associated with a second fraction. The method also includes inserting the masked first fraction into mask adder circuitry of a partial product tree. The method also includes combining the masked first fraction with partial products of the partial product tree, the partial products having a value of zero. The method further includes combining the masked first fraction and the second fraction.Type: ApplicationFiled: August 13, 2019Publication date: February 18, 2021Inventors: Michael Klein, Nicol Hofmann, Kerstin Claudia Schelm, Tina Babinsky
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Publication number: 20210034328Abstract: A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Stefan Payer, Silvia Melitta Mueller, Nicol Hofmann, Razvan Peter Figuli
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Publication number: 20210034325Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Nicol Hofmann, Michael Klein, Petra Leber, Kerstin Claudia Schelm
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Patent number: 10890622Abstract: Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.Type: GrantFiled: April 29, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefan Payer, Michael Klein, Nicol Hofmann, Cedric Lichtenau
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Publication number: 20200412388Abstract: A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Inventors: Nicol Hofmann, Michael Klein, Kerstin Claudia Schelm, Razvan Peter Figuli
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Publication number: 20200348908Abstract: Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Kerstin Claudia Schelm, Petra Leber, Nicol Hofmann, Michael Klein
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Publication number: 20200341839Abstract: Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Stefan Payer, Michael Klein, Nicol Hofmann, Cedric Lichtenau
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Patent number: 10747819Abstract: A processor unit can rapidly search a string of characters. The processor unit includes vector registers each having M vector elements, each having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each upper diagonal of the matrix of comparators and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. The processor unit result generating logic generates, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string.Type: GrantFiled: April 20, 2018Date of Patent: August 18, 2020Assignee: International Business Machines CorporationInventors: Stefan Payer, Razvan Peter Figuli, Cedric Lichtenau, Nicol Hofmann
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Publication number: 20190325083Abstract: A processor unit can rapidly search a string of characters. The processor unit includes vector registers each having M vector elements, each having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each upper diagonal of the matrix of comparators and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. The processor unit result generating logic generates, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string.Type: ApplicationFiled: April 20, 2018Publication date: October 24, 2019Inventors: Stefan Payer, Razvan Peter Figuli, Cedric Lichtenau, Nicol Hofmann
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Patent number: 10324816Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: March 8, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
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Patent number: 10318395Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: November 13, 2017Date of Patent: June 11, 2019Assignee: INTERNATION BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach