Abstract: An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract: A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V?); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135?; N3s, 135?) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135?; 135?). A memory device using the sensing circuit and a method are also provided.

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract: A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit integrates an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage depending on the polarization state of the storage capacitor.

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V?); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135?; N3s, 135?) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135?; 135?). A memory device using the sensing circuit and a method are also provided.

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line.

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line.