Abstract: A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA. A first configuration data set implements a first design in a first area of the FPGA, a second design in a second, non-overlapping area, and at least one bus macro that defines a bus interface between the first design and the second design. The bus interface includes a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines. A second configuration data set implements a modified version of the first design in the first area and does not implement any version of the second design. The FPGA is configured with the first configuration data set, and then partially configured with the second configuration data set.

Abstract: A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area.

Abstract: A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area.

Abstract: The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called "slices". Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.