Patents by Inventor Nicolas POSSEME

Nicolas POSSEME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180315614
    Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).
    Type: Application
    Filed: April 24, 2018
    Publication date: November 1, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas POSSEME
  • Publication number: 20180286697
    Abstract: A method for etching an assembled block copolymer layer including first and second polymer phases, in which the etching method includes exposing the assembled block copolymer layer to a plasma so as to etch the first polymer phase and simultaneously to deposit a carbon layer on the second polymer phase, wherein the plasma is formed from a gas mixture including a depolymerising gas and an etching gas selected among the hydrocarbons.
    Type: Application
    Filed: September 9, 2016
    Publication date: October 4, 2018
    Inventors: Nicolas POSSEME, Aurélien SARRAZIN
  • Patent number: 10062602
    Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 28, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS—Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc
    Inventors: Nicolas Posseme, Sebastien Barnola, Olivier Joubert, Srinivas Nemani, Laurent Vallier
  • Patent number: 10056470
    Abstract: A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 21, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Christian Arvet, Nicolas Posseme
  • Publication number: 20180233366
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 16, 2018
    Applicant: COMMISSARIAT L'ENERGIE A TOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia NOURI, Stefan Landis, Nicolas Posseme
  • Patent number: 10043890
    Abstract: A method is provided for forming spacers of a gate of a field effect transistor, the gate including flanks and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer covering the gate; after the step of forming, at least one step of modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light ions; and at least one step of removing the modified dielectric layer including a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture including at least one first component with a hydrofluoric acid base that transforms the modified dielectric layer into non-volatile residue, and removing the non-volatile residue via a wet clean performed after the dry etching or a thermal annealing of sublimation performed after or during the dry etching.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 7, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Nicolas Posseme
  • Patent number: 10026657
    Abstract: A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 17, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Laurent Grenouillet
  • Patent number: 10014386
    Abstract: There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 3, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Christian Arvet
  • Patent number: 9953807
    Abstract: A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 24, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Sebastien Barnola, Thibaut David, Lamia Nouri, Nicolas Posseme
  • Patent number: 9947768
    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method including forming a dielectric layer covering the gate of the transistor; modifying the dielectric layer by putting the dielectric layer into presence with a plasma formed from a gas formed from at least one first non-carbonated gaseous component of which dissociation generates light ions and a second gaseous component comprising at least one species favoring dissociation of the first component in order to form the light ions, wherein a gas ratio between the first component and the second component is between 1:19 and 19:1.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 17, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 9947541
    Abstract: A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x?0.2, and having a pH less than or equal to 1.5.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 17, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Maxime Garcia-Barros, Nicolas Posseme
  • Patent number: 9934973
    Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior pattern
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 3, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Nicolas Posseme, Sebastien Barnola, Thibaut David, Lamia Nouri
  • Publication number: 20180012766
    Abstract: A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x?0.2, and having a pH less than or equal to 1.5.
    Type: Application
    Filed: June 20, 2017
    Publication date: January 11, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Maxime Garcia-Barros, Nicolas Posseme
  • Publication number: 20180001582
    Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least; a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411?, 411?) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step;) c) a step of removing (461, 462) the modified zones (41
    Type: Application
    Filed: December 22, 2015
    Publication date: January 4, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Stephan LANDIS, Lamia NOURI
  • Publication number: 20170372967
    Abstract: A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 28, 2017
    Inventors: Laurent BRUNET, Nicolas POSSEME
  • Publication number: 20170372904
    Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior pattern
    Type: Application
    Filed: December 22, 2015
    Publication date: December 28, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stephan LANDIS, Nicolas POSSEME, Sebastien BARNOLA, Thibaut DAVID, Lamia NOURI
  • Patent number: 9853124
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Publication number: 20170363954
    Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patte
    Type: Application
    Filed: December 22, 2015
    Publication date: December 21, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stephan LANDIS, Nicolas POSSEME, Lamia NOURI
  • Publication number: 20170358502
    Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: December 14, 2017
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Laurent GRENOUILLET, Sebastien BARNOLA, Marie-Anne JAUD, Jerome MAZURIER, Nicolas POSSEME
  • Publication number: 20170352522
    Abstract: A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.
    Type: Application
    Filed: June 2, 2017
    Publication date: December 7, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan LANDIS, Sebastien BARNOLA, Thibaut DAVID, Lamia NOURI, Nicolas POSSEME