Abstract: A probe head with a cylindrical portion and an oblique truncated portion angled downward toward a high-powered electronic device under testing. The probe head has a proximal end comprising an oblique truncated cone portion angled relative to the longitudinal axis at an input angle and has an analog signal input. The probe head has a digital signal output provided on the distal end of the housing.

Abstract: A method for combining multiple different data processing, artificial intelligence and/or machine learning frameworks for execution by a target hardware includes extracting one or more computation graphs from each of the different frameworks. The computation graphs are combined into a fused computation graph. Memcopy operations are removed at edges between the computation graphs of the different frameworks. Memory spaces for computations in the fused computation graph are remapped to memory spaces of the target hardware.

Abstract: A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning, for each input edge of each node in the tensor computation graph, a tensor shape, assigning, for each dimension of the input and output of each layer of the tensor computation graph, a loop primitive, and generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops.

Abstract: A computer-implemented method for compiling a neural network with tensors having dynamic shapes includes parsing the neural network using a set of global virtual dimension identifications (IDs) that define the dynamic shapes of one or more of the tensors of the neural network. The method further includes performing shape checks while building a computation graph using the set of global virtual dimension IDs, and generating a runtime code of the neural network based on the computation graph.

Abstract: A method for optimizing a neural network includes identifying parameters of a computation graph of the neural network that depend on input data as a computation part, and parameters of the computation graph that are independent of the input data as a pre-evaluation part. The method splits the computation graph into the pre-evaluation part and the computation part, and generates and applies a wrapper that performs a transparent mapping of data layouts of the pre-evaluation part.

Abstract: A method for providing an asynchronous execution queue for accelerator hardware includes replacing a malloc operation in an execution queue to be sent to an accelerator with an asynchronous malloc operation that returns a unique reference pointer. Execution of the asynchronous malloc operation in the execution queue by the accelerator allocates a requested memory size and adds an entry to a look-up table accessible by the accelerator that maps the reference pointer to a corresponding memory address.

Abstract: A system, method, and computer-readable medium for synthesizing zero-copy sparse matrix factorization operations in heterogeneous compute systems are provided. The system includes a host and an accelerator device. The host device is configured to divide an input matrix into a plurality of blocks which are transferred to a memory of the accelerator device. The host device is also configured to generate at least one index buffer that includes pointers to the block in the accelerator's memory, where each index buffer represents a frontal matrix associated with a matrix decomposition algorithm. The host processor is configured to receive one or more kernels configured to process the index buffer(s) on an accelerator device. The index buffers are processed by the accelerator device and the modified block data is written back to a memory of the host device to generate a factorized output matrix.

Abstract: A method for accelerating a neural network includes identifying neural network layers that meet a locality constraint. Code is generated to implement depth-first processing for different hardware based on the identified neural network layers. The generated code is used to perform the depth-first processing on the neural network based on the generated code.

Abstract: A method for combining multiple different data processing, artificial intelligence and/or machine learning frameworks for execution by a target hardware includes extracting one or more computation graphs from each of the different frameworks. The computation graphs are combined into a fused computation graph. Memcopy operations are removed at edges between the computation graphs of the different frameworks. Memory spaces for computations in the fused computation graph are remapped to memory spaces of the target hardware.

Abstract: An assembly including a hydraulic device around a second axis of rotation by means of a proximal rolling-element bearing and a distal rolling-element bearing, the hydraulic device including a shaft, a multi-lobe cam, a cylinder block and a distributor, and a pivoting element adapted to be mounted on an axle, and movable in rotation relative to the hydraulic device around a first axis of rotation. Views along a plane defined by the second axis of rotation and the first axis of rotation, the proximal rolling-element bearing and the distal rolling-element bearing are positioned on either side of the first axis of rotation, in that the cylinder block is positioned between the first axis of rotation and the proximal rolling-element bearing.

Abstract: A method for providing an asynchronous execution queue for accelerator hardware includes replacing a malloc operation in an execution queue to be sent to an accelerator with an asynchronous malloc operation that returns a unique reference pointer. Execution of the asynchronous malloc operation in the execution queue by the accelerator allocates a requested memory size and adds an entry to a look-up table accessible by the accelerator that maps the reference pointer to a corresponding memory address.

Abstract: A method of memory remapping for utilizing dense neural network computations with a sparse neural network includes the step of densifying the sparse neural network. The input and output data is remapped onto the densified neural network. The dense neural network computations are utilized for a prediction using the remapped input and output data.

Abstract: A method for processing a neural network includes performing a decompression step before executing operations associated with a block of layers of the neural network, performing a compression step after executing operations associated with the block of layers of a neural network, gathering performance indicators for the executing the operations associated with the block of layers of the neural network, and determining whether target performance metrics have been met with a compression format used for at least one of the decompression step and the compression step.

Abstract: A method for accelerating a neural network includes identifying neural network layers that meet a locality constraint. Code is generated to implement depth-first processing for different hardware based on the identified neural network layers. The generated code is used to perform the depth-first processing on the neural network based on the generated code.

Abstract: The present invention relates to a method for quantifying residual host cell genomic DNA in recombinant protein biologics using quantitative real time PCR.