Patents by Inventor Nidhi Nidhi

Nidhi Nidhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11587924
    Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11581313
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
  • Patent number: 11527532
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 11502191
    Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Johann Christian Rode, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid M. Hafez
  • Publication number: 20220359697
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
  • Patent number: 11450617
    Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 11437483
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
  • Patent number: 11387328
    Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Nidhi Nidhi
  • Publication number: 20220157729
    Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Publication number: 20220068910
    Abstract: Disclosed herein are IC structures, packages, and devices that include linearization devices integrated on the same support structure as III-N transistors. A linearization device may be any suitable device that may exhibit behavior complementary to that of a III-N transistor so that a combined behavior of the III-N transistor and the linearization device includes less nonlinearity than the behavior of the III-N transistor alone. Linearization devices may be implemented as, e.g., one-sided diodes, two-sided diodes, or P-type transistors. Integrating linearization devices on the same support structure with III-N transistors advantageously provides an integrated solution based on III-N transistor technology, thus providing a viable approach to reducing or eliminating nonlinear behavior of III-N transistors.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Johann Christian Rode, Rahul Ramaswamy, Marko Radosavljevic, Nidhi Nidhi, Walid M. Hafez, Paul B. Fischer, Sansaptak Dasgupta
  • Patent number: 11264329
    Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Publication number: 20210280683
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
  • Publication number: 20210193844
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a source, a drain, and a semiconductor channel between the source and the drain. In an embodiment, the semiconductor channel has a non-uniform strain through a thickness of the semiconductor channel. In an embodiment, the semiconductor device further comprises a gate stack around the semiconductor channel.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Babak FALLAHAZAD, Hsiao-Yuan WANG, Ting CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Nidhi NIDHI, Walid M. HAFEZ
  • Publication number: 20210184032
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Walid M. HAFEZ, Hsu-Yu CHANG, Ting CHANG, Babak FALLAHAZAD, Tanuj TRIVEDI, Jeong Dong KIM
  • Publication number: 20210183857
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, the semiconductor device comprises a substrate, and a first transistor over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel above the substrate, a first gate dielectric surrounding the first semiconductor channel, and a first gate electrode over the first gate dielectric. In an embodiment, the semiconductor device further comprises a second transistor over the substrate. In an embodiment, the second transistor comprises a second semiconductor channel above the substrate, a second gate dielectric surrounding the second semiconductor channel, where the second gate dielectric is different than the first gate dielectric, and a second gate electrode over the second gate dielectric, where the first gate electrode and the second gate electrode comprise the same material.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Walid M. HAFEZ, Rahul RAMASWAMY, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Publication number: 20210184000
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Publication number: 20210184001
    Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Ting CHANG, Walid M. HAFEZ, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Publication number: 20210184045
    Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Nidhi NIDHI, Ting CHANG, Hsu-Yu CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Babak FALLAHAZAD
  • Publication number: 20210183850
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Walid M. HAFEZ, Hsu-Yu CHANG, Ting CHANG, Babak FALLAHAZAD, Tanuj TRIVEDI, Jeong Dong KIM, Ayan KAR, Benjamin ORR
  • Publication number: 20210184051
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Ting CHANG, Walid M. HAFEZ, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI