Abstract: An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided An output for an RF output signal is obtained from the parallel connection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.

Abstract: A RF power amplifier circuit has at least one power transistor and a protection circuit protecting the power transistor against high voltages that lead to a destructive breakdown of the transistor. The circuit comprises a power transistor (2), a biasing circuit (6) biasing the power transistor; a peak detector (8) measuring the output voltage of the power transistor; and a comparator circuit (12) connected to the peak detector (8) and designed to reduce the base current of the power transistor (2) when controlled by the peak detector (8).

Abstract: An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided. An output for an RF output signal is obtained from the parallelconnection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.

Abstract: A RF power amplifier circuit has at least one power transistor and a protection circuit protecting the power transistor against high voltages that lead to a destructive breakdown of the transistor. The circuit comprises a power transistor (2), a biasing circuit (6) biasing the power transistor; a peak detector (8) measuring the output voltage of the power transistor; and a comparator circuit (12) connected to the peak detector (8) and designed to reduce the base current of the power transistor (2) when controlled by the peak detector (8).

Abstract: The invention relates to an erasable non-volatile memory in which a diode is formed at each point of intersection between the x-selection lines (Ki) and y-selection lines (Rj), of which diode the anode and cathode are conductively connected to the x- and y-selection lines. The diodes are formed in hydrogenated amorphous silicon or silicon compounds such as amorphous Si−xGex. Writing takes place by means of a current pulse through selected diodes. The current in the forward direction becomes much lower, for example a few hundred times lower, than in diodes which are not selected, probably owing to degradation in the semiconductor material. The diodes may be returned to their original state again (i.e. be erased) through heating, for example at a temperature of 200° C. during 100 minutes. Preferably, the diodes are formed by Schottky diodes because the characteristic in the reverse direction does not (substantially) change in this type of diode.