Patents by Inventor Niels Oeschler

Niels Oeschler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600658
    Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andre Wedi, Guido Boenig, Niels Oeschler, Christian Stahlhut
  • Publication number: 20200027752
    Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Andre Wedi, Guido Boenig, Niels Oeschler, Christian Stahlhut
  • Patent number: 10475668
    Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andre Wedi, Guido Boenig, Niels Oeschler, Christian Stahlhut
  • Publication number: 20190006193
    Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Andre Wedi, Guido Boenig, Niels Oeschler, Christian Stahlhut
  • Patent number: 10020278
    Abstract: A semiconductor chip includes a semiconductor body having a bottom side and a top side opposite the bottom side, and passivation arranged on the top side. The semiconductor chip is positioned on the carrier by picking the semiconductor chip and placing the semiconductor chip on the carrier, and pressing the semiconductor chip onto the carrier by a pressing force in a pressing direction, such that the pressing force acts on the semiconductor chip only above one or more continuous chip metallization sections arranged on the top side. Each of the one or more continuous chip metallization sections includes an annularly closed edge section which has a minimum width of more than zero in each direction perpendicular to the pressing direction. The pressing force does not act on the semiconductor chip above any of the edge sections.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventor: Niels Oeschler
  • Patent number: 9741639
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Publication number: 20170025373
    Abstract: A semiconductor chip includes a semiconductor body having a bottom side and a top side opposite the bottom side, and passivation arranged on the top side. The semiconductor chip is positioned on the carrier by picking the semiconductor chip and placing the semiconductor chip on the carrier, and pressing the semiconductor chip onto the carrier by a pressing force in a pressing direction, such that the pressing force acts on the semiconductor chip only above one or more continuous chip metallization sections arranged on the top side. Each of the one or more continuous chip metallization sections includes an annularly closed edge section which has a minimum width of more than zero in each direction perpendicular to the pressing direction. The pressing force does not act on the semiconductor chip above any of the edge sections.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Inventor: Niels Oeschler
  • Patent number: 8835299
    Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roland Speckels, Lars Böwer, Nicolas Heuck, Niels Oeschler
  • Patent number: 8736052
    Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Niels Oeschler, Kirill Trunov, Roland Speckels
  • Publication number: 20140077376
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Publication number: 20140061909
    Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Roland Speckels, Lars Böwer, Nicolas Heuck, Niels Oeschler
  • Patent number: 8466548
    Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 18, 2013
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Niels Oeschler, Alexander Ciliox
  • Publication number: 20130049204
    Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Niels Oeschler, Kirill Trunov, Roland Speckels
  • Publication number: 20120306087
    Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Reinhold Bayerer, Niels Oeschler, Alexander Ciliox