Patents by Inventor Nien-Ting Ho
Nien-Ting Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150249142Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.Type: ApplicationFiled: April 28, 2015Publication date: September 3, 2015Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
-
Patent number: 9048254Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.Type: GrantFiled: December 2, 2009Date of Patent: June 2, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
-
Patent number: 8993390Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.Type: GrantFiled: May 15, 2014Date of Patent: March 31, 2015Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
-
Publication number: 20150061042Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsun-Min Cheng, Nien-Ting Ho, Chien-Hao Chen, Ching-Yun Chang, Hsin-Fu Huang, Min-Chuan Tsai, Chi-Yuan Sun, Chi-Mao Hsu
-
Patent number: 8883650Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.Type: GrantFiled: January 24, 2008Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
-
Patent number: 8877635Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.Type: GrantFiled: June 10, 2013Date of Patent: November 4, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
-
Publication number: 20140306273Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.Type: ApplicationFiled: April 16, 2013Publication date: October 16, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
-
Patent number: 8860150Abstract: The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer.Type: GrantFiled: December 10, 2009Date of Patent: October 14, 2014Assignee: United Microelectronics Corp.Inventors: Chin-Fu Lin, Nien-Ting Ho, Chun-Hsien Lin, Chih-Hao Yu, Cheng-Hsien Chou
-
Publication number: 20140248762Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.Type: ApplicationFiled: May 15, 2014Publication date: September 4, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
-
Publication number: 20140239419Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Min-Chuan Tsai, Wei-Yu Chen, Nien-Ting Ho, Tsun-Min Cheng, Chi-Mao Hsu
-
Patent number: 8815738Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.Type: GrantFiled: July 10, 2012Date of Patent: August 26, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Chang Hsu, Bor-Shyang Liao, Kuo-Chih Lai, Nien-Ting Ho, Chi-Mao Hsu, Shu-Min Huang, Min-Chung Cheng
-
Patent number: 8766319Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.Type: GrantFiled: April 26, 2012Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
-
Publication number: 20140017888Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Bor-Shyang Liao, Kuo-Chih Lai, Nien-Ting Ho, Chi-Mao Hsu, Shu-Min Huang, Min-Chung Cheng
-
Publication number: 20130288456Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
-
Publication number: 20130273736Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
-
Patent number: 8541303Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.Type: GrantFiled: September 28, 2011Date of Patent: September 24, 2013Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
-
Patent number: 8507350Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.Type: GrantFiled: September 21, 2011Date of Patent: August 13, 2013Assignee: United Microelectronics CorporationInventors: Chien-Chung Huang, Nien-Ting Ho
-
Publication number: 20130078800Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
-
Publication number: 20130071981Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chien-Chung HUANG, Nien-Ting HO
-
Patent number: 8344465Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at middle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.Type: GrantFiled: March 20, 2012Date of Patent: January 1, 2013Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang